Vertical GaN Transistor Technology Landscape 2026
Vertical GaN Transistor Technology Landscape 2026
Vertical GaN transistors have demonstrated 1.3 kV breakdown and 1.93 mΩ·cm² on-resistance on 4-inch free-standing GaN wafers. China’s filing trajectory and monolithic integration patents from Guangzhou Research Institute of Xidian University signal the next competitive frontier.
Vertical Architecture Unlocks GaN’s Full Power Potential
Vertical GaN transistors route current perpendicular to the wafer surface, placing source and drain on opposite faces of the semiconductor stack. This decouples breakdown voltage from chip area — a structural limitation that constrains lateral AlGaN/GaN HEMTs, where voltage-blocking distance consumes horizontal chip real estate.
Five core device families are identified in this dataset: Current Aperture Vertical Electron Transistors (CAVETs), trench MOSFETs with buried gate electrodes, vertical-channel JFETs with p-GaN regrowth, vertical fin-FETs with wrap-around gate structures, and emerging complementary FETs (CFETs) integrating n- and p-channel devices monolithically on a single die.
Bulk (free-standing) GaN substrates and GaN-on-silicon are the two primary substrate platforms identified. MOCVD is the dominant epitaxial growth technique. Specific on-resistances below 2 mΩ·cm² and breakdown voltages exceeding 1.3 kV have been experimentally demonstrated on free-standing GaN substrates, confirming the material advantage over silicon and competing with SiC in the 650 V–1.2 kV class.
The most recent filings (2025–2026) from Guangzhou Research Institute of Xidian University signal a pivot from isolated device demonstrations toward system-level monolithic integration — co-integrating lateral GaN driver transistors with vertical GaN power switches on a single die to eliminate parasitic inductances of discrete packaging. Robert Bosch GmbH’s automotive-oriented filings address field shielding reliability, targeting the 650 V–1.2 kV inverter class.
From Foundational Patents to Monolithic Integration
The dataset reveals three distinct innovation eras: a foundational period (2001–2015) dominated by Japanese and Korean assignees, a concentrated development phase (2017–2021) anchored by academic research, and a maturation phase (2022–2026) characterised by Chinese institutional filings on system-level integration and European automotive reliability patents.
Vertical GaN Device Architecture Cluster Distribution
Trench MOSFET and JFET/fin-FET clusters account for the largest share of identifiable architecture-specific filings in the dataset, with CAVET and monolithic integration as the most active emerging clusters.
↗ Click bars to exploreVertical GaN Innovation Timeline by Filing Era
Filing activity is heavily concentrated in the 2022–2026 window, driven primarily by Chinese institutional assignees, with the 2017–2021 academic research era forming the technical foundation.
↗ Click bars to exploreWhere Vertical GaN Transistors Are Deployed
Patents and literature in this dataset identify four primary application domains for vertical GaN transistors: EV powertrains and industrial power conversion, 5G base station power supply, aerospace and space systems, and monolithic power ICs integrating driver and power stages on a single die.
EV Powertrains & Industrial Power
Vertical GaN devices with breakdown voltages above 1.2 kV enable compact, thermally efficient inverters and on-board chargers for electric vehicles. Guangzhou Research Institute of Xidian University’s 2026 monolithic integration patent explicitly cites DC-DC converters for new-energy vehicles and photovoltaic inverters as target applications. Academic literature from 2020 covers GaN HEMTs across aircraft, rail, and heavy-duty vehicle electrification.
Power Conversion5G Base Station Power Supply
GaN transistors hold a dominant position in RF power amplifiers at mmW frequencies per the 2019 GaN power electronics roadmap and 2020 literature on GaN in 5G. Vertical GaN architectures are increasingly relevant for base station power supply modules. A 2025 CN patent from Huzhou Gallium-Aoyue Technology describes CNT-based vertical interconnects that reduce parasitic inductance by more than 95%, directly enabling high-frequency vertical GaN power supply operation.
RF & CommunicationsAerospace & Geostationary Satellites
A 6-year in-orbit experiment on the Alphasat geostationary satellite, reported in 2022 academic literature, confirmed GaN transistors’ robustness under cumulative ionizing radiation doses in geostationary orbit, validating their use in space power systems. A 2020 academic paper covers GaN technology-based DC/DC converters for hybrid UAVs, extending the application scope to unmanned aerial vehicles.
Aerospace SystemsMonolithic GaN Power ICs
Guangzhou Research Institute of Xidian University’s 2026 patent describes a monolithically integrated CMOS-driven GaN vertical device where lateral low-voltage driver transistors and vertical high-voltage power switches share a single die, eliminating discrete package parasitics. Their 2025 GaN vertical complementary FET (VCFET) and inverter patents realize CMOS-equivalent logic by stacking n- and p-channel vertical GaN transistors, addressing the absence of high-performance p-channel GaN devices.
Monolithic Power ICsWho Holds the Core Vertical GaN IP
Innovation is distributed across US academic institutions, Chinese research institutes and startups, and European automotive Tier-1 suppliers. Arizona State University and Guangzhou Research Institute of Xidian University are the most active assignees by filing count in this dataset, with China showing the most accelerating recent trajectory (2022–2026).
Top Assignees by Vertical GaN Patent Filing Count (Dataset)
↗ Click bars to exploreArizona Board of Regents (ASU)
Arizona Board of Regents on behalf of Arizona State University holds at least 4 active US patents filed between 2022 and 2024, all covering GaN vertical-channel junction field-effect transistors fabricated via MOCVD regrowth of p-GaN on fin-patterned channels defined by electron beam lithography. Key patents include a 2022 base filing, a 2022 continuation, a 2023 grant, and a 2024 divisional — establishing a cluster of regrowth-based fin patterning claims. IP strategists entering the US market should conduct freedom-to-operate analysis around these active filings.
United StatesGuangzhou R.I. of Xidian University
Guangzhou Research Institute of Xidian University (Xidian University Guangzhou Research Institute) has filed multiple CN patents between 2025 and 2026, covering GaN vertical complementary FETs (VCFETs), a GaN VCFET inverter, monolithically integrated CMOS-driven GaN vertical devices, and lateral-vertical monolithic integration structures with fabrication methods and equivalent circuits. These filings represent the forward edge of system-level vertical GaN integration and target applications including DC-DC converters for new-energy vehicles and photovoltaic inverters. International product developers targeting the Chinese market should monitor these broad-scope filings as they mature.
China — CNFive Signals Shaping the Next Phase of Vertical GaN
The most recent filings (2025–2026) reveal a shift from device-level demonstrations toward system-level differentiation. Five distinct emerging directions are identifiable in this dataset, spanning monolithic integration, complementary logic, advanced packaging, substrate scaling, and gate dielectric innovation.
Monolithic Lateral-Vertical Integration (2025–2026)
Guangzhou Research Institute of Xidian University’s 2026 patents describe co-integration of lateral GaN low-voltage driver transistors with vertical GaN high-voltage power switches on a single die. The process flows are specifically designed to minimize conflicts between lateral HEMT and vertical transistor fabrication steps. This approach eliminates the parasitic inductances introduced by discrete packaging and is explicitly cited for DC-DC converters in new-energy vehicles and photovoltaic inverters.
GaN Vertical Complementary FETs (VCFETs) for Logic
Two VCFET-and-inverter patents were filed by Guangzhou Research Institute of Xidian University in February and November 2025. These devices stack n-channel and p-channel GaN vertical transistors to realize CMOS-equivalent logic functions. This addresses the long-standing absence of high-performance p-channel GaN devices that has blocked the realization of full GaN integrated circuits, enabling mixed-signal and logic functionality in a GaN-native process.
Trench MOSFET vs. Vertical JFET: Key Dimensions
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| Dimension | Vertical Trench MOSFET | Vertical-Channel JFET (p-GaN Regrowth) |
|---|---|---|
| Gate Control Mechanism | MOS gate dielectric (e.g. Al₂O₃) on trench sidewall inversion channel | p-GaN regrown around fin sidewall creates depletion-mode pinch-off gate |
| Operation Mode | Normally-off (enhancement-mode) | Depletion-mode (normally-on); enhancement-mode achievable via fin geometry |
| Key Challenge | Achieving stable, low-trap MOS interface in GaN; gate oxide trapping | Precise fin patterning via electron beam lithography; p-GaN regrowth uniformity |
| Demonstrated Performance | 1.3 kV breakdown, 1.93 mΩ·cm² on 4-inch free-standing GaN wafer (2022) | Threshold voltages and channel pinch-off demonstrated; regrown large-area fins reported |
| Gate Dielectric Innovation | (NH₄)₂S passivation and Al₂O₃ gate dielectrics; La-doped HZO via plasma-enhanced ALD (2024–2025) | No gate dielectric required — avoids MOS interface complexity |
| Primary Academic/IP Assignee | Multiple — Robert Bosch GmbH (US/DE, 2022–2024), Shenzhen University (CN, 2022), academic groups | Arizona Board of Regents / Arizona State University (US, 2022–2024) — 4 active patents |
| Substrate Platform | Free-standing GaN (4-inch demonstrated); GaN-on-Si (reliability study, 2021) | Bulk GaN substrate; MOCVD regrowth process |
| System Integration Outlook | Targeted for automotive 650 V–1.2 kV inverter class; Robert Bosch filings address field shielding reliability | Building block for vertical fin-FET arrays; applicable to high-density switching |
Frequently Asked Questions: Vertical GaN Transistors
According to 2022 academic literature in this dataset, vertical GaN-based trench MOSFETs fabricated on a 4-inch free-standing GaN wafer demonstrated 1.3 kV breakdown voltage and 1.93 mΩ·cm² specific on-resistance.
The five core families are: (1) Current Aperture Vertical Electron Transistors (CAVETs) with a current blocking layer aperture; (2) trench MOSFETs with gate electrodes buried in vertical trenches; (3) vertical-channel JFETs with p-GaN regrowth; (4) vertical fin-FETs with wrap-around gate structures; and (5) emerging complementary FETs (CFETs) integrating n- and p-channel devices monolithically.
Arizona Board of Regents on behalf of Arizona State University is the most active single assignee for vertical GaN transistor patents in this dataset, with at least 4 active US patents (2022, 2022, 2023, 2024) all covering MOCVD-regrown p-GaN JFET processes.
The 2025 CN patent from Huzhou Gallium-Aoyue Technology Co., Ltd. describes a GaN chip packaging structure using vertical carbon nanotube (CNT) arrays on the gate region, claiming more than 95% reduction in parasitic inductance and resolution of coefficient of thermal expansion (CTE) mismatch for high-frequency vertical GaN operation.
A 6-year in-orbit experiment on the Alphasat geostationary satellite, reported in 2022 academic literature, confirmed GaN transistors’ robustness under cumulative ionizing radiation doses in geostationary orbit, validating their use in space power systems.
The literature in this dataset consistently identifies bulk (free-standing) GaN substrates and GaN-on-silicon as the two primary substrate platforms, with MOCVD as the dominant epitaxial growth technique. The 2021 academic review highlights 200 mm CTE-matched GaN-on-silicon as a pathway toward foundry-compatible, high-volume manufacturing.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.