Vertical GaN Trench MOSFET Technology Landscape 2026
Vertical GaN Trench MOSFET Technology Landscape 2026
Vertical GaN trench MOSFETs have demonstrated breakdown voltages of 1.3–3.0 kV and specific on-resistances of 1.2–2.1 mΩ·cm² on 4-inch wafers. Patent activity across the US, China, and Taiwan signals intensifying commercial competition in this wide-bandgap power device class.
Vertical GaN Trench MOSFETs: Architecture, Performance, and IP Activity
Vertical GaN trench MOSFETs route current perpendicular to the wafer surface through a p-GaN channel region formed along the sidewalls of an etched trench, with the gate dielectric deposited inside the trench and the drain contact placed at the substrate backside. This architecture decouples breakdown voltage from chip area, unlike lateral HEMTs where both are constrained by planar geometry.
The retrieved literature confirms experimentally demonstrated specific on-resistance values in the range of 1.2–2.1 mΩ·cm² and breakdown voltages of 1.3–3.0 kV, representing figures of merit that exceed silicon and approach SiC benchmarks for the 1–3 kV class. A 1.2 kV vertical GaN FinFET demonstrated MHz-range switching superiority versus commercial Si and SiC devices in 2018.
Three principal sub-domains are covered in this dataset: trench MOSFET structures with insulated gate dielectrics (SiO₂, Al₂O₃, Ta₂O₅, or bilayer stacks); current-aperture vertical electron transistors (CAVETs) that combine HEMT-like channel mobility with vertical current routing; and vertical fin and nanowire architectures with wrap-around gates for tight electrostatic control.
In this dataset, filings and publications span 2002–2026, with more than 75% of entries concentrated in the 2018–2026 window. China exhibits the highest filing count in retrieved records (>10 CN patents), distributed across institutions including Xidian University, Nanjing University, Peking University, and Zhejiang Xinke Semiconductor.
Filing Trends and Technology Cluster Distribution in Retrieved GaN Trench MOSFET Records
Analysis of retrieved patent and literature records reveals that more than 75% of entries are concentrated in the 2018–2026 window, with four distinct technology clusters identified: trench MOSFET with p-GaN channel, CAVET structures, vertical fin/3D gate architectures, and gate stack engineering.
Patent Filings by Technology Cluster — Vertical GaN Trench MOSFET (Dataset Snapshot)
In this dataset, trench MOSFET with p-GaN channel and insulated gate accounts for the largest share of patent filings, followed by gate stack engineering and CAVET structures.
↗ Click bars to exploreFiling Activity by Period — Vertical GaN Trench MOSFET Retrieved Records
In this dataset, patent and literature filings accelerated sharply after 2018, with the 2022–2026 period containing the largest concentration of retrieved records across all technology clusters.
↗ Click bars to exploreKey Application Domains for Vertical GaN Trench MOSFETs
Retrieved patent and literature records identify four principal application domains for vertical GaN trench MOSFETs: medium-voltage power conversion for EVs and grid infrastructure, monolithic power ICs with on-chip CMOS drivers, solid-state lighting integration, and next-generation ultra-wide bandgap device development.
Electric Vehicles & Grid Infrastructure
The dominant application pull in this dataset is medium-voltage (600 V–3 kV) power conversion for electric vehicles, industrial motor drives, and grid-tied inverters, explicitly identified in the 2018 GaN Power Electronics Roadmap as the inflection point for vertical GaN commercialization. The Xidian University Guangzhou Research Institute’s 2025–2026 filings on CMOS-driven GaN vertical devices explicitly target electric vehicles, grid infrastructure, and high-speed rail. Multiple patent filers frame their 1.2 kV class devices as drop-in SiC competitors.
Power ElectronicsMonolithic Power ICs & Smart Gate Drivers
Xidian University Guangzhou Research Institute filed two CN patents in 2025 and 2026 disclosing CMOS-driven GaN vertical transistors and vertical complementary FETs (VCFETs) in a single epitaxial process flow, targeting elimination of the external Si CMOS driver. The VCFET concept stacks n-type and p-type vertical GaN devices to reduce chip area by approximately 50% versus lateral complementary arrangements. These represent the sharpest emerging integration direction in retrieved records.
Monolithic IntegrationSolid-State Lighting Integration
Nanjing University has filed and received granted CN patents in 2023 and 2025 (both active) for monolithic integration of vertical trench MOSFETs with LED structures on the same GaN chip, where the MOSFET gate controls LED driving current. This niche application targets compact smart lighting modules and represents a unique device co-integration approach not found in other assignees’ portfolios in this dataset.
Solid-State LightingNext-Generation Ga₂O₃ Power Devices
The Research Foundation for the State University of New York filed a PCT patent in 2026 for a Ga₂O₃ vertical trench MOSFET with a Mg-doped current blocking layer, directly transposing device architecture developed for GaN vertical trench MOSFETs to Ga₂O₃ (~8.6 eV bandgap versus 3.4 eV for GaN). This is the first evidence in this dataset of GaN trench MOSFET architecture transfer to the next-generation ultra-wide bandgap space, potentially opening IP freedom-to-operate questions for future entrants.
Ultra-Wide BandgapKey Patent Assignees in Vertical GaN Trench MOSFET — Retrieved Records Snapshot
In retrieved records, The Hong Kong University of Science and Technology holds the most concentrated single-assignee position on core trench MOSFET architecture with 4 active patents across US and TW jurisdictions, while Chinese institutions collectively account for the highest filing volume in this dataset, distributed across integration applications and gate dielectric innovation.
Top Assignees by Filing Count — Vertical GaN Trench MOSFET (Dataset Snapshot)
↗ Click bars to exploreHong Kong Univ. of Science & Technology
Holds 4 active patents across US (2022, 2025) and TW (2023, 2024) jurisdictions, all covering asymmetric or non-uniform p-GaN channel doping (two-step or multi-step Mg doping) to independently engineer threshold voltage and channel resistance in GaN vertical trench MOSFETs. This represents the most concentrated and geographically broad single-assignee patent position on the core trench MOSFET architecture in retrieved records. A CN patent (2022) on the same vertical trench MOSFET manufacturing method is also included in the portfolio.
Hong Kong / United StatesSixPoint Materials, Inc.
Holds 3 filings spanning US (2024, pending), WO (2024), and IN (2025, pending) jurisdictions, all covering a GaN trench MOSFET fabrication method using multi-step ion implantation to form an n-type region within Mg-doped p-GaN below the trench bottom, combined with multi-step dry etching to expose p-GaN sidewalls for channel formation. The geographically distributed filing strategy across US, WO, and India indicates early-stage international IP protection expansion for this fabrication approach.
United StatesFive Emerging Directions in Vertical GaN Trench MOSFET Technology (2023–2026)
Based on the most recent filings and publications in this dataset from 2023–2026, five distinct emerging directions have been identified, spanning monolithic integration, substrate scaling, Mg-diffusion control, architecture transfer to Ga₂O₃, and high-κ gate dielectric alternatives.
Monolithic GaN Power ICs with On-Chip CMOS Drivers
Two patents from Xidian University Guangzhou Research Institute (2025 and 2026) disclose CMOS-driven GaN vertical transistors and vertical complementary FETs (VCFETs) in a single chip. The VCFET concept stacks n-type and p-type vertical GaN devices to reduce chip area by approximately 50% versus lateral complementary arrangements. This direction could enable the GaN power IC market to bypass the external Si driver requirement entirely.
200 mm CMOS-Compatible Processing on Engineered Substrates
A 2023 literature report demonstrates 8.5 µm thick GaN drift layers on 200 mm QST (polycrystalline AlN core, QROMIS) substrates achieving greater than 750 V hard breakdown, directly addressing the cost barrier of native GaN substrates. This aligns with the broader industry effort to make vertical GaN manufacturable on large-diameter Si-compatible tooling and signals a manufacturing tipping point for the technology.
Vertical GaN Trench MOSFET vs. SiC MOSFET: Key Performance and IP Dimensions
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| Dimension | Vertical GaN Trench MOSFET | SiC MOSFET (Reference) |
|---|---|---|
| Breakdown Voltage | 1.3–3.0 kV demonstrated (dataset records) | Comparable 1–3 kV commercial class (referenced in dataset) |
| Specific On-Resistance | 1.2–2.1 mΩ·cm² demonstrated | Approached by GaN per 2018 FinFET switching FOM paper |
| Switching Speed | MHz-range demonstrated in 1.2 kV 5 A FinFET (2018) | Surpassed by GaN FinFET at comparable voltage (per dataset) |
| Substrate Diameter | 4-inch free-standing GaN wafer (2022 device); 200 mm engineered QST substrate (2023) | 150–200 mm commercially available |
| Gate Dielectric | SiO₂, Al₂O₃, bilayer Al₂O₃/SiO₂, Ta₂O₅ (high-κ emerging) | SiO₂ standard; reliability well-established |
| MOS Interface Quality | Primary reliability bottleneck; bilayer reduces leakage by 2 orders of magnitude vs. single Al₂O₃ | Mature interface passivation processes |
| Threshold Voltage (Vth) | +3.15 V demonstrated (4-inch wafer, 2022); asymmetric doping enables independent Vth tuning | Positive Vth (enhancement mode) standard |
| IP Landscape | Core device IP concentrated at Hong Kong UST; gate stack IP fragmented across multiple assignees (dataset snapshot) | Mature IP landscape; multiple commercial licensors |
Frequently Asked Questions: Vertical GaN Trench MOSFET Technology
Retrieved literature confirms experimentally demonstrated breakdown voltages in the range of 1.3–3.0 kV. Specifically, a 2022 study on 4-inch free-standing GaN wafers showed 1306 V, and a 2022 TCAD simulation of a stepped doping trench CAVET projected 3024 V. These figures place GaN in the 1–3 kV class alongside SiC.
The dominant reliability bottleneck identified in retrieved records is MOS interface quality on etched GaN sidewalls, which determines threshold voltage stability and channel mobility. A 2020 study demonstrated that a bilayer gate insulator (2.5 nm Al₂O₃ + 35 nm SiO₂) reduces gate leakage by two orders of magnitude versus a single Al₂O₃ layer and delivers 11 V higher off-state drain breakdown voltage.
In retrieved records, The Hong Kong University of Science and Technology holds the most concentrated single-assignee position, with 4 active patents across US (2022, 2025) and TW (2023, 2024) jurisdictions, all covering asymmetric or non-uniform p-GaN channel doping to independently engineer threshold voltage and channel resistance. A CN patent from 2022 on the same manufacturing method is also part of this portfolio.
A current-aperture vertical electron transistor (CAVET) inserts a p-GaN current blocking layer (CBL) beneath the channel aperture to direct electron flow vertically, combining HEMT-like channel mobility with vertical current routing. Unlike a trench MOSFET where current flows through an inverted p-GaN channel under a gate dielectric, the CAVET uses the aperture geometry to confine current. A 2023 study demonstrated 3.2 kA/cm² drain current and Ron,sp of 1.2 mΩ·cm² in a trench CAVET using a low-temperature GaN Mg stopping layer.
Yes. A 2023 literature report in retrieved records demonstrates 8.5 µm thick GaN drift layers on 200 mm QST substrates (polycrystalline AlN core, QROMIS) achieving greater than 750 V hard breakdown. This addresses the cost barrier of native GaN substrates and aligns with efforts to make vertical GaN manufacturable on large-diameter Si-compatible tooling.
The Research Foundation for the State University of New York filed a PCT patent in 2026 for a Ga₂O₃ vertical trench MOSFET with a Mg-doped current blocking layer, directly transposing the GaN trench MOSFET architecture to Ga₂O₃ (~8.6 eV bandgap vs. 3.4 eV for GaN). This is the first evidence in this dataset of GaN trench architecture transfer to the ultra-wide bandgap space, potentially opening IP freedom-to-operate questions for future entrants in next-generation power devices.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.