Vertical Power MOSFET Packaging Technology Landscape 2026
Vertical Power MOSFET Packaging Technology Landscape 2026
Vertical power MOSFET packaging is accelerating across four major sub-domains, from leadframe-based discrete packages to system-level vertical power delivery for AI compute loads exceeding 1,000 A. Patent filings from 2002 to 2026 document this 24-year innovation arc.
Four Sub-Domains Defining Vertical MOSFET Packaging
Vertical power MOSFETs route current perpendicular to the die surface — from the drain contact on the bottom face through an epitaxial drift region to the source contact on the top face. This architecture creates unique packaging challenges: the drain metallization suits direct thermal attachment to a heatsink or leadframe, while source and gate contacts must be accessed via wirebonds, metal clips, or flip-chip interconnects.
The field subdivides into four primary sub-domains: leadframe-based discrete and multi-die packages, vertically stacked and 3D-integrated power modules, integrated and intelligent power modules co-packaging control silicon with power silicon, and vertical power delivery architectures at the system level targeting ultra-high-current delivery for high-performance compute.
Patent filings in this dataset span 2002 to 2026, revealing three distinct eras: a foundational era (2002–2010) establishing core architectures, a development and diversification era (2010–2020) proliferating package form factors and multi-die integration, and an advanced integration era (2020–2026) dominated by data center AI compute requirements driving vertical power delivery architectures.
Innovation in this dataset is concentrated among a small number of large players. Infineon Technologies, Alpha and Omega Semiconductor, Vishay-Siliconix, and Google LLC together account for approximately 65% of patent records. However, emerging Chinese assignees and research institutions such as Zhejiang University and the University of Central Florida signal a broader distribution of innovation activity in recent filings.
Patent Activity by Technology Cluster and Era
Three distinct innovation eras are visible in this dataset: a foundational era (2002–2010), a development and diversification era (2010–2020), and an advanced integration era (2020–2026) with 8+ results from 2024–2026 alone. Four technology clusters account for the full filing population.
Patent Filings by Technology Cluster — Vertical Power MOSFET Packaging
Leadframe-based multi-die co-packaging remains the most populated cluster historically, while system-level vertical power delivery is the fastest-growing cluster in the 2020–2026 period.
↗ Click bars to exploreFiling Activity by Innovation Era — Vertical Power MOSFET Packaging
The advanced integration era (2020–2026) shows concentrated activity with 8+ filings from 2024–2026 alone, driven by Google LLC and Intel Corporation data center compute patents.
↗ Click bars to exploreKey Application Domains for Vertical Power MOSFET Packaging
Vertical power MOSFET packaging innovations are deployed across five application domains in this dataset, from AI data center compute to automotive EV powertrain, consumer electronics, industrial motor drives, and aerospace.
Data Center & AI/ML Compute
The fastest-growing demand driver in this dataset, represented by 7+ recent results. CPU/GPU/ASIC power loads exceeding 1,000 A have made vertical power delivery a practical necessity. Google LLC’s TLVR patent family (US and EP, 2022–2025) and Intel Corporation’s system-on-package filing (US, 2025) achieve up to 10% net power reduction at iso-performance with passives contained within the die footprint.
Vertical Power DeliveryAutomotive & EV Powertrain
The primary established market for vertical MOSFET die architectures and molded IPM packages. Literature results (2016, 2020) confirm double-side cooling, sintered die bonding, and high-temperature operation as dominant requirements. Huangshan Baoni’s CN filings (2018) employ graphene-enhanced thermal interface materials and direct bonded copper substrates for automotive thermal management.
Intelligent Power ModuleIndustrial Motor Drives
Infineon Technologies Americas Corp.’s PQFN patent family (US and EP, 2014–2017) targets three-phase inverter applications, integrating multi-phase U/V/W power switch arrays, gate drivers, bootstrap diodes, and current reconstruction logic in a single leadframe package. Delta Electronics (Shanghai) Co., Ltd.’s packaging structure for power modules (EP, 2024) uses multi-layer carrier substrates with stacked metal layers for industrial converter applications.
Leadframe PackageConsumer Electronics & Mobile
Apple Inc.’s low-profile power conversion module patents (US, 2014, 2018) address point-of-load DC/DC converters for ultraportable notebooks, tablets, and smartphones under severe height constraints. Vishay-Siliconix’s complete power management system (multiple US, EP, WO filings, 2007–2015) and Huawei Technologies’ flip-chip MOSFET power supply module (US, 2012) target compact DC/DC integration for mobile platforms.
Surface Mount PackageLeading Assignees in Vertical Power MOSFET Packaging Patents
Innovation in this dataset is concentrated among a small number of large players: Infineon Technologies Americas Corp. leads with approximately 10 filings, followed by Google LLC and Vishay-Siliconix at approximately 6 each, and Alpha and Omega Semiconductor at approximately 5. Together with Infineon Technologies AG, these entities account for approximately 65% of retrieved patent records.
Top Assignees by Filing Count — Vertical Power MOSFET Packaging
↗ Click bars to exploreInfineon Technologies Americas Corp.
Infineon Technologies Americas Corp. holds approximately 10 filings in this dataset, spanning 2002 to 2017, making it the highest-volume assignee in the vertical power MOSFET packaging landscape. Key filings cover Power MOSFET with Integrated Drivers in a Common Package (US, 2002, 2003), Power Converter Package Including Top-Drain Configured Power FET (US/EP, 2014–2016), and the PQFN package series integrating bootstrap diodes and single-shunt inverter circuits (US, 2014–2017). These patents collectively define the core IP estate for leadframe-based multi-die IPM and PQFN packages used in motor drive and inverter applications.
United StatesGoogle LLC
Google LLC holds approximately 6 filings in this dataset, concentrated in the 2022–2024 period, making it the leading assignee in the system-level vertical power delivery cluster. Its trans-inductor voltage regulator (TLVR) patent family spans US, EP, and WO jurisdictions (2022–2024), covering integration of VR modules in vertical power delivery stacks and scalable modular multi-MHz bandwidth TLVR configurations for AI accelerator compute loads exceeding 1,000 A. A 2025 US continuation further extends the family’s prosecution timeline.
United StatesFour Forward-Looking Technology Directions from 2023–2026 Filings
The most recent filings (2023–2026) in this dataset signal four distinct forward-looking directions: vertically-oriented die architectures, MHz-bandwidth scalable VR integration, space-constrained system-on-package with embedded passives, and graphene-enhanced thermal interface materials in IPM packaging.
Vertically-Oriented Die for Radical Current Density Improvement
Monolithic Power Systems’ Power Modules with Vertically-Oriented Power Dies (US, 2026) moves beyond conventional flat die mounting by physically orienting power dies vertically within the module. This approach targets current density improvement beyond the ~0.72 A/mm² benchmark of a conventional 9×10 mm two-phase DrMOS module. The structural concept was previously explored by MyPaq Holdings (US, 2006) at the converter level but is now being applied to DrMOS-type integrated modules, representing a potential discontinuity in current density benchmarks for server and networking VR applications.
MHz-Bandwidth Scalable TLVR for AI Compute VR Integration
Google LLC’s Scalable and Modular Multi-MHz Bandwidth TLVR in Vertical Power Delivery (WO, 2024) pushes trans-inductor voltage regulators toward modular multi-phase configurations with multi-MHz switching bandwidth. The packaging challenge is integrating trans-inductors, decoupling capacitors, and MOSFET switches within the strict x/y/z envelope of a processor package. Intel Corporation’s companion SoP filing (US, 2025) embeds passives within the die footprint and achieves up to 10% power reduction at iso-performance versus conventional lateral solutions.
Leadframe-Based IPM vs. System-Level Vertical Power Delivery: A Direct Comparison
Click any row to explore further.
| Dimension | Leadframe-Based IPM (PQFN/DrMOS) | System-Level Vertical Power Delivery (TLVR/SoP) |
|---|---|---|
| Primary Assignees | Infineon Technologies Americas Corp., Alpha and Omega Semiconductor, Vishay-Siliconix | Google LLC, Intel Corporation, Monolithic Power Systems |
| Filing Period in Dataset | 2002–2023 | 2020–2026 |
| Target Application | Motor drives, three-phase inverters, consumer DC/DC, automotive IPM | AI/ML data center, CPU/GPU/ASIC compute loads exceeding 1,000 A |
| Interconnect Approach | Stamped copper leadframe, copper clips, aluminum wirebonds, metal interconnection plates | Trans-inductor topology, vertical power path from motherboard bottom to ASIC top |
| Thermal Management | Exposed die paddle PCB soldering, graphene TIM on DBC substrates (CN filings) | Passives embedded within die footprint; up to 10% power reduction at iso-performance |
| Current Density Benchmark | ~0.72 A/mm² for conventional 9×10 mm two-phase DrMOS module | Targets loads exceeding 1,000 A per processor complex via vertical stack |
| Jurisdiction Coverage | US, EP, WO, TW, CN | US, EP, WO |
| Key Package Form Factors | PQFN, DrMOS, molded IPM, surface-mount complete power management | VR module beneath processor die, system-on-package (SoP), TLVR integrated stack |
Frequently Asked Questions: Vertical Power MOSFET Packaging
The four primary sub-domains are: (1) leadframe-based discrete and multi-die packages using stamped metal leadframes with wirebonds or copper clips; (2) vertically stacked and 3D-integrated power modules minimizing parasitic inductance and footprint; (3) integrated/intelligent power modules (IPMs) combining power switches with gate drive and protection ICs on a common substrate or leadframe; and (4) vertical power delivery architectures at the system level integrating voltage regulator functions beneath or within high-performance compute packages.
Infineon Technologies Americas Corp. leads with approximately 10 filings in this dataset, spanning 2002 to 2017, covering PQFN packages, IPM designs, top-drain configured power FET packages, and power MOSFETs with integrated drivers in a common package.
The 2024–2026 cluster is dominated by Google LLC’s vertical power delivery TLVR patent family and Intel Corporation’s space-constrained system-on-package filings, both targeting data center AI compute. Monolithic Power Systems also filed on power modules with vertically-oriented power dies in 2026. The primary driver is CPU/GPU/ASIC power loads exceeding 1,000 A per processor complex.
The conventional benchmark cited in the dataset is approximately 0.72 A/mm² for a 9×10 mm two-phase DrMOS module. Monolithic Power Systems’ Power Modules with Vertically-Oriented Power Dies (US, 2026) is described as targeting current density improvement beyond this figure by physically orienting power dies vertically within the module.
Chinese assignees including Huangshan Baoni, Shanghai Haxin, Xinyu Microelectronics (Suzhou), and Chongqing Wanguo Semiconductor Technology are filing in CN-jurisdiction patents on power module packaging. Notably, graphene thin films on direct bonded copper substrates for IPM thermal management — filed by Huangshan Baoni (CN, 2018) and Anhui Jixin Microelectronics Technology (CN, 2025) — have no counterpart filings in the US or EP jurisdictions within this dataset, suggesting an IP whitespace for non-Chinese assignees.
Intel Corporation’s Vertical Power Delivery in Space-Constrained System-on-Package (US, 2025) embeds passives within the die footprint, eliminates deep trench capacitor costs, and achieves up to 10% net power reduction at iso-performance compared to conventional lateral solutions, while maintaining compatibility with standard datacenter baseboard infrastructure.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.