Via Last TSV Technology Landscape 2026 | PatSnap Eureka
Via Last Through Silicon Via Technology Landscape 2026
Via-last TSV technology is transitioning from a packaging convenience to a system architecture primitive. This dataset snapshot covers fabrication mechanisms, key assignees, and emerging directions from 2008 to 2026.
Via-Last TSV: From MEMS Packaging to 3D System Architecture
Via-last through silicon via (TSV) technology defines a manufacturing sequence in which vertical interconnects are etched, lined, and filled after active device layer completion. This approach leaves standard CMOS foundry processes undisturbed and enables post-bond thinning and TSV reveal as final steps, making it well suited for heterogeneous die stacking.
Core technical mechanisms in this dataset span deep reactive-ion etching (DRIE) for high aspect-ratio via formation at pitches as fine as 30 µm, conformal polyimide liner systems for stress relief at 10:1 aspect ratios (11 µm diameter), and copper electroplating fill. IBM demonstrated copper TSVs at 13 µm pitch in 45 nm SOI-CMOS EDRAM with up to 11,000 TSVs per wafer pair.
Application domains in this dataset range from MEMS and sensor packaging — the earliest and most mature — to CMOS image sensors qualified at AEC-Q100 Grade 2 for automotive use on 12″ wafers at 65 nm node, high-performance logic-memory stacking, flip-chip LED submounts, and the most recently emerging domain: co-packaged optics with TSV diameters of 2–10 µm at 10–50 µm pitch.
In retrieved records, IBM and Qualcomm are the most prominent patent assignees in via-last TSV, with IBM active across post-bond integration and backside PDN architectures (2014, 2024) and Qualcomm filing a TSV bridge interconnect in EP jurisdiction (2020). Amity University Hyderabad represents an emerging Indian IP actor with a 2026 co-packaged optics platform patent in this dataset.
Filing Activity and Technology Clusters in Via-Last TSV
The via-last TSV dataset spans five named assignees and multiple institutional contributors from 2008 to 2026, with identifiable clusters in DRIE-based fabrication, advanced liner materials, and backside power delivery architectures.
TSV Patent Assignees by Filing Count (Dataset Snapshot)
IBM and Qualcomm are the most frequently appearing patent assignees in this dataset, each with multiple distinct records spanning post-bond integration, backside PDN, and bridge interconnect approaches.
↗ Click bars to exploreVia-Last TSV Records by Year of Publication/Filing (Dataset Snapshot)
Records in this dataset cluster in three periods — 2008–2009 (foundational), 2014–2020 (CMOS scaling), and 2022–2026 (materials and backside integration) — reflecting distinct innovation phases.
↗ Click bars to exploreKey Via-Last TSV Deployment Domains: From MEMS to Co-Packaged Optics
Via-last TSV technology has been deployed across six distinct application domains in this dataset, spanning MEMS sensor packaging, CMOS image sensors, high-performance computing logic-memory stacks, LED submounts, wide 3D data bus architectures, and co-packaged optics for AI systems.
MEMS and Sensor Packaging
The earliest and most mature domain in this dataset, documented by Silex Microsystems (2008) achieving 30 µm pitch TSVs in substrates up to 600 µm thick with 36 mΩ median resistance for 300 µm thick TSVs. Fraunhofer IZM contributed foundational work on 3D wafer-level heterogeneous integration for optical MEMS and inertial sensors in 2008. Via-last TSVs eliminate wire bonds and reduce die area for MEMS wafer-level packaging.
Wafer-Level PackagingLogic-Memory Stacking HPC
IBM’s 2014 demonstration integrated copper TSVs at 13 µm pitch with 45 nm SOI-CMOS EDRAM technology, achieving up to 11,000 TSVs per wafer pair with up to four additional metal levels formed post-bonding, targeting cache memory integration for high-performance server processors. This represents the field’s transition from research-grade flows to manufacturing-compatible stacking. Average TSV resistance was reported at ~0.14 mΩ for copper-filled vias.
3D IC IntegrationAutomotive CMOS Image Sensors
Via-last TSV-based wafer-level chip-scale packaging (WLCSP) has been qualified for backside-illuminated CMOS image sensors at AEC-Q100 Grade 2 for automotive use, on 12″ wafers at 65 nm node, achieving greater than 98% yield and 120 dB dynamic range (2020). This qualification demonstrates via-last TSV process maturity for high-reliability automotive electronics. The technology enables compact packaging without wire bonds for camera module integration.
Automotive ElectronicsCo-Packaged Optics AI Systems
Amity University Hyderabad’s 2026 Indian patent combines TSV (2–10 µm diameter, 10–50 µm pitch) with copper-to-copper hybrid bonding at 10 µm pitch for photonic integrated circuit (PIC) and electronic integrated circuit (EIC) chiplet co-integration, targeting bandwidth beyond the 20–30 Tb/s passive silicon interposer ceiling. A minimum 500 µm keepout from optical waveguides is specified for optical signal integrity. This represents a ~3–5× pitch reduction from the 2014-era 13 µm IBM benchmark.
Advanced AI PackagingKey Patent Assignees in Via-Last TSV — Dataset Snapshot
In retrieved records, IBM is the most frequently appearing patent assignee with two distinct via-last TSV patents spanning 2014–2024, followed by Qualcomm, Amity University Hyderabad, GlobalFoundries, and Synopsys each with one patent in this dataset. US jurisdiction dominates in retrieved records, with an emerging Indian filing in 2026.
Via-Last TSV Patent Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreInternational Business Machines Corporation
IBM holds two via-last TSV patents in this dataset spanning 2014–2024 (US jurisdiction). The 2014 record covers copper TSV at 13 µm pitch integrated with 45 nm SOI-CMOS EDRAM technology, achieving up to 11,000 TSVs per wafer pair. The 2024 US patent introduces an upper TSV (uTSV) extending from a backside power distribution network through single-crystal silicon layers, representing a new architectural role for via-last TSVs as power delivery rails decoupled from signal routing.
United StatesQualcomm Incorporated
Qualcomm holds one TSV-related patent in this dataset, filed in EP jurisdiction in 2020, covering a through silicon via bridge interconnect for advanced chiplet packaging architectures. This patent addresses multi-die connectivity using TSV-based bridge structures, relevant to chiplet-based system-in-package designs. The filing reflects Qualcomm’s focus on advanced packaging interconnect for mobile and compute platforms.
EP JurisdictionFour Forward Directions in Via-Last TSV Innovation (2022–2026)
The most recent filings and publications in this dataset signal four distinct forward directions: sub-10 µm pitch for co-packaged optics, backside TSV as power delivery rail, high entropy alloy solders for lower bonding temperatures, and polymer-lined HAR TSVs for KOZ reduction.
Sub-10 µm TSV Pitch for Co-Packaged Optics
Amity University’s 2026 IN filing specifies TSV diameters of 2–10 µm at 10–50 µm pitch with a minimum 500 µm keepout from optical waveguides, directly addressing optical signal integrity in photonic-electronic co-integration. This represents a ~3–5× pitch reduction from the 2014-era 13 µm IBM benchmark. The filing targets bandwidth beyond the 20–30 Tb/s passive silicon interposer ceiling through copper-to-copper hybrid bonding at 10 µm pitch combined with TSV routing.
Backside TSV as Dedicated Power Delivery Rail
IBM’s 2024 US patent introduces an upper TSV (uTSV) extending from a backside power distribution network through single-crystal silicon transistor layers to additional interconnects, decoupling power and signal routing into separate vertical domains. This architectural departure from traditional via-last usage aligns with the semiconductor industry’s backside power delivery roadmap. Via-last TSVs in this configuration function as power rails rather than signal interconnects.
Via-Last vs. Via-Middle TSV: Key Dimension Comparison
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| Dimension | Via-Last TSV | Via-Middle TSV |
|---|---|---|
| Fabrication Sequence | Etched, lined, and filled after active device layer completion; enables post-bond thinning and TSV reveal as final steps | Formed after front-end of line (FEOL) but before back-end of line (BEOL) metal layers |
| CMOS Process Compatibility | Standard CMOS foundry processes remain undisturbed; no thermal budget impact on active devices | Must be compatible with BEOL thermal budget; integrated within the metal stack build-up |
| Demonstrated Pitch | 13 µm (IBM, 45 nm SOI-CMOS, 2014); 30 µm (Silex MEMS, 2008); 2–10 µm diameter targeted (Amity, 2026) | Not directly characterised in this dataset |
| Aspect Ratio | Up to 10:1 demonstrated (11 µm diameter, polyimide liner, 2022); substrate thicknesses up to 600 µm (Silex, 2008) | Not directly characterised in this dataset |
| Liner Material | SiO₂ (conventional); polyimide via vacuum-assisted spin coating for stress-critical HAR applications (2022) | Typically oxide or nitride; polymer liners not reported in this dataset for via-middle |
| Key Application Domains | MEMS/WLP, logic-memory stacking (HPC), BSI CIS automotive, LED submounts, co-packaged optics, backside PDN | N/A — not covered in this dataset |
| Stress Management | KOZ reduction targeted via polyimide liner; thermomechanical stress a leading yield-limiting mechanism on thin substrates | N/A — not covered in this dataset |
| Resistance (reported) | 36 mΩ median (300 µm TSV, PVD metallization, Silex); ~0.14 mΩ (Cu-filled, IBM 45 nm node) | N/A — not covered in this dataset |
Frequently Asked Questions: Via-Last Through Silicon Via Technology
Via-last TSV defines a manufacturing sequence in which through-silicon vias are etched, lined, and filled after the completion of active device layers, in contrast to via-first (before FEOL) and via-middle (after FEOL but before BEOL) approaches. This sequence allows standard CMOS foundry processes to remain undisturbed and enables post-bond thinning and TSV reveal as final steps, making it particularly suited for stacking heterogeneous die combinations.
IBM demonstrated copper TSVs at 13 µm pitch integrated with 45 nm SOI-CMOS EDRAM technology in 2014, achieving up to 11,000 TSVs per wafer pair. The Silex process achieved 30 µm pitch on substrates up to 600 µm thick in 2008. Amity University’s 2026 Indian patent targets TSV diameters of 2–10 µm at 10–50 µm pitch for co-packaged optics applications.
Polyimide liners deposited via vacuum-assisted spin coating enable conformal lining at 10:1 aspect ratios (11 µm diameter), addressing thermomechanical stress — a leading yield-limiting mechanism in via-last flows applied to thin substrates. The approach targets sub-12 µm diameter vias while reducing stress and enabling higher integration density. A plasma bombardment step achieves surface activation critical to liner adhesion, and semi-additive RDL formation on photosensitive polyimide isolates signal routing from the via stress field.
IBM’s 2024 US patent introduces an upper TSV (uTSV) that extends from a backside power distribution network through single-crystal silicon transistor layers to additional interconnects, effectively decoupling power and signal routing into separate vertical domains. This represents a structural departure from traditional via-last usage and aligns with the semiconductor industry’s backside power delivery roadmap.
A charge-recycling 64/128-bit stacked I/O bus using dense TSV arrays at 40 µm pitch in standard 65 nm CMOS achieved 0.160 pJ/bit power efficiency. This represents a system-level optimisation lever independent of further pitch scaling, offering an alternative path to power-efficient 3D interconnect without requiring via dimension reduction.
In retrieved records, US jurisdiction is dominant, with IBM (two patents, 2014 and 2024), GlobalFoundries (one patent, 2016 at 14 nm node), and Synopsys (one patent, 2011) all filing in the US. Qualcomm filed one TSV bridge interconnect patent in EP jurisdiction in 2020. Amity University Hyderabad represents an emerging Indian IP actor with a 2026 co-packaged optics platform patent filed in IN jurisdiction.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.