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Run your analysis now →https://www.patsnap.com/resources/blog/rd-blog/wafer-defect-engineering-and-gettering-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Silicon Wafer & Epitaxy · Patent LandscapeWafer defect engineering and gettering patents: mapping who controls denuded-zone and intrinsic gettering claims
- 52.0% of all 2,146 records sit with just five assignees, so the core intrinsic-gettering and denuded-zone claim space is already tightly held.
- Filing has flattened, not grown 2021 to 2024 filings held at 13 a year, a 0% change across that span, after a 2017 peak of 36.
- C30B crystal growth reaches 51.3% of records while H10P sits at 33.1%, showing defect control is claimed as much at the crystal-pulling stage as at the device stage.
2,146
Published Records
52%
Top-5 Share of All Records
0%
Filing Growth 2021→2024
US
Leading Jurisdiction
Filing growth compares 2021 (13 records) with 2024 (13) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 2,146 records in scope (CR5), not by the ranked leaders only.
Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Field Overview
What this landscape covers
Wafer defect engineering and gettering covers the methods used to control point defects, void defects and metal contamination in silicon wafers before and during device fabrication. Core techniques include intrinsic gettering through internal oxygen precipitation, formation of a denuded zone near the wafer surface, control of crystal-originated particles, and management of interstitial oxygen and thermal donor concentrations that affect minority carrier lifetime. These are foundational quality controls for logic, memory and power device fabs, not a niche sub-field.
The dataset spans 2,146 published records filed between 2015 and 2026, drawn from a search string combining intrinsic gettering, crystal-originated particle and wafer defect engineering terms with void defect, denuded zone, interstitial oxygen, thermal donor, metal contamination and minority carrier lifetime terms. Publication lags filing by roughly 18 months, so the most recent one to two years understate actual filing activity.
Filing activity and IPC composition, 2015-2026
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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The Numbers
Filing trends and technology composition
Two views matter here: how filing volume has moved year on year, and how the claim space splits across IPC subclasses. Both point to a mature, consolidated field rather than an expanding one.
Filing trend: a 2017 peak, then a plateau
Filings peaked in 2017 at 36 and have since settled into a flatter pattern; the 2021-2024 window shows 13 filings in both years, a 0% change, indicating steady rather than accelerating activity. Treat 2025 and 2026 figures as provisional given the usual publication lag.
IPC composition: crystal growth and device claims dominate
H01L semiconductor devices appears in 69.7% of records and C30B crystal growth in 51.3%, confirming that defect control is claimed both at the crystal-pulling stage and downstream at the device stage. H10P follows at 33.1%, while G01N material analysis, H10B memory manufacture and B32B layered products each sit under 5%, marking thinner, more specialised claim territory.
Shares are the percentage of the 2,146 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.
Go deeper on Wafer Defect Engineering and Gettering with Eureka
This page is one run against one query. Ask Eureka your own question about wafer defect engineering and gettering and every answer comes back with the patent numbers behind it.
Try EurekaFoundational Claims
The patent that named the technique
Representative Record
US4597804A — Methods of forming denuded zone in wafer by intrinsic gettering and forming bipolar transistor therein
FUJITSU LIMITED
A variety of methods are applicable to production of semiconductor devices in which the active layer is produced in a denuded zone which is thin and free of defects. This denuded zone in combination with a high concentration of crystalline defects contained in a deep layer of the semiconductor device allows the semiconductor device to enjoy the function of the intrinsic gettering effect. Improvements described include a decrease in overall production time and removal of limitations due to the oxygen concentration of a wafer, achieved by increasing and/or decreasing the annealing temperature gradually at a predetermined rate.Filed by Fujitsu Limited, 1986-07-01 — one of the earliest documented descriptions of combining a denuded zone with intrinsic gettering in a single process flow.
Most-cited records in this field
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6815352B1 | Silicon focus ring and method for producing the same | 476 |
| 2 | US7217320B2 | Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking f… | 450 |
| 3 | US5919302A | Low defect density vacancy dominated silicon | 210 |
| 4 | US5994761A | Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor | 169 |
| 5 | US6368938B1 | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate | 165 |
| 6 | WO1998045507A1 | Low defect density, ideal oxygen precipitating silicon | 161 |
| 7 | US5773152A | SOI substrate having a high heavy metal gettering effect for semiconductor device | 134 |
| 8 | US5611855A | Method for manufacturing a calibration wafer having a microdefect-free layer of a precisely predetermined dep… | 131 |
| 9 | US20010037761A1 | Epitaxial silicon wafer free from autodoping and backside halo and a method and apparatus for the preparation… | 128 |
| 10 | US5401669A | Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation… | 123 |
Ranked by citation count within the searched corpus; older records accumulate more citations simply by being available longer, so treat this as a signal of influence rather than current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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What the numbers mean for a filing decision
The concentration, plateau and IPC split each carry a practical implication for anyone deciding where to file next or who to watch.
Concentration
52.0% of 2,146 records
held by the top five assignees
The core claim space is already crowded
Just five assignees hold roughly half of all records in scope, meaning the fundamental intrinsic gettering and denuded-zone process claims are largely occupied. New entrants filing broad process claims in this exact territory face a dense prior-art landscape rather than open ground.
Top 10 combined reach 68.1% of records
Momentum
13 → 13 filings
2021 to 2024, 0% change
A plateau, not a decline
Filing volume has held flat rather than falling over the most recent complete three-year window. High filing density earlier in the field's history means claim space is occupied, not that the underlying technology has stopped evolving.
2017 remains the peak filing year at 36
Technology split
69.7% vs 51.3%
H01L vs C30B share of records
Claims split between crystal growth and device stages
Nearly seven in ten records touch H01L device claims, and just over half touch C30B crystal-growth claims, so defect control is fought over at two separate manufacturing stages rather than one. Smaller categories such as G01N testing and B32B layered products remain comparatively thin.
H10P appears in 33.1% of records
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Co-filing patterns
| Assignee | Co-assignee | Shared families |
|---|---|---|
| SUMCO Corporation | HOURAI MASATAKA | 9 |
| SUMCO Corporation | ONO TOSHIAKI | 7 |
| Toshiba Corporation | Toshiba Microelectronics Corporation | 6 |
| SunEdison, Inc. | BANAN MOHSEN | 5 |
| SUMCO Corporation | UMENO SHIGERU | 5 |
| SUMCO Corporation | SUGIMURA WATARU | 5 |
| Shin-Etsu Handotai Co., Ltd. | Praditek Co., Ltd. | 5 |
| Toshiba Corporation | Toshiba Ceramics Co., Ltd. | 5 |
Co-assignee pairs are limited to 10 identified pairings in this dataset, concentrated around a small number of named inventors working with a single major assignee, suggesting most filing here is done independently rather than through joint ventures.
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Who's Filing
The assignee landscape
The ranking covers 100 companies counted by patent family, the full set the data endpoint returns rather than a curated top tier. Filing is heavily front-loaded: the leader holds 414 records, fifth place holds 92, and tenth place holds 57, a steep drop-off that continues through the rest of the ranked list.
Leader
414 records
held by the top-ranked assignee
A single assignee dominates the field
The leading assignee's record count is more than four times that of the fifth-placed company, indicating a long-running, deliberate filing program in crystal growth and gettering processes rather than incidental coverage.
Fifth place holds 92 records
Mid-tier drop-off
92 → 57 records
fifth place to tenth place
A steep gradient below the leader
The gap from fifth to tenth place is smaller than from first to fifth, but still substantial, showing a tier of established silicon wafer manufacturers rather than a single-company monopoly.
Top 10 combined hold 68.1% of all records
Long tail
100 companies ranked
in the assignee ranking
A long tail beyond the concentrated core
Beyond the top ten, filing spreads thinly across many companies with far fewer records each, typical of a field where device makers and equipment suppliers file defensively around a smaller set of dominant crystal-growth patents.
Recent-year activity across named leaders shows 0 filings in the latest year for several
Recent-year filing momentum
| Assignee | Recent year | YoY |
|---|---|---|
| SunEdison, Inc. | 0 | — |
| SUMCO Corporation | 0 | — |
| Shin-Etsu Handotai Co., Ltd. | 0 | — |
| Fujitsu Limited | 0 | — |
| Siltronic AG | 0 | -100% |
| Toshiba Corporation | 0 | — |
| NEC Corporation | 0 | — |
| SUMITOMO MITSUBISHI SILICON CORP | 0 | — |
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Next Steps
Where to take this analysis
The figures above describe the field as a whole. Turning them into a filing or freedom-to-operate decision means drilling into specific claim families and specific competitors.
Map claims against a specific process step
Cross-reference the H01L and C30B claim splits against your own process flow to see whether your defect-control step falls in the crowded core or the thinner adjacent branches.
Explore in EurekaTrack the leading assignees' recent activity
Recent-year momentum for several named leaders shows a slowdown, which may signal a shift toward trade-secret protection or a pause worth watching before it reverses.
Run an assignee watch in EurekaSource: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ
Common questions on wafer defect engineering patents
Intrinsic gettering is a defect-control technique that uses a wafer's own internal oxygen precipitation to trap metal contaminants away from the active device region. It typically works alongside formation of a denuded zone, a thin, defect-free layer near the surface where devices are actually built. The technique is documented as far back as the 1980s, with early process patents describing controlled annealing to form the denuded zone while relying on a deeper defect-rich layer for the gettering effect.
Filing in this field is concentrated: the top five assignees together account for 52.0% of the 2,146 records in scope, and the top ten account for 68.1%. The leading assignee alone holds 414 records, well ahead of the fifth-placed company at 92, which points to a small group of established silicon wafer and semiconductor manufacturers driving most of the documented filing activity. Beyond the top ten, coverage spreads thinly across a long tail of smaller filers.
Filing has plateaued rather than grown in the most recent complete years: 2021 and 2024 both recorded 13 filings, a 0% change across that span, after an earlier peak of 36 filings in 2017. Because publication lags filing by roughly 18 months, figures for 2025 and 2026 are still incomplete and should not be read as a decline. The honest read is a mature field with steady rather than expanding filing activity.
US4597804A describes methods for forming a denuded zone in a silicon wafer through intrinsic gettering, then building a bipolar transistor in that zone, filed by Fujitsu and dating from 1986. Its claims cover process improvements including gradual annealing temperature ramps that reduce production time and relax constraints on starting wafer oxygen concentration. Anyone working with combined denuded-zone-plus-intrinsic-gettering process flows should check their annealing schedule against this record's specific temperature-ramp language.
The IPC composition data shows most claim density sitting in H01L device claims (69.7% of records) and C30B crystal-growth claims (51.3%), while categories like G01N material analysis and testing, H10B memory device manufacture, and B32B layered products each cover under 5% of records. That gap suggests thinner coverage around in-line defect measurement protocols, memory-specific denuded zone tuning, and layered or bonded-wafer gettering approaches. These branches are worth a closer freedom-to-operate check before assuming they are as crowded as the core crystal-growth claims.
Answers are grounded in the same dataset. Derived from a Patsnap search on Wafer Defect Engineering and Gettering covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.