Wafer Level Chip Scale Packaging Patents: Leaders & Trends 2026
- 46.5% concentration. The five most active filers account for 2,017 of the 4,342 records in scope — a field with a clear head but still open beyond it.
- H10W now rivals the core class. 55.4% of records carry an H10W subclass alongside the 90.4% in H01L, showing the field has split into a distinct redistribution/interconnect track.
- Filing has cooled, not collapsed. From 2021 to 2024 — the last complete year — filings moved from 286 to 249, a 13% pullback, after peaking at 411 in 2018.
Filing growth compares 2021 (286 records) with 2024 (249) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 4,342 records in scope (CR5), not by the ranked leaders only.
What the wafer level chip scale packaging patent record shows
Wafer level chip scale packaging (WLCSP) sits at the intersection of front-end wafer processing and back-end assembly: redistribution layers, polymer dielectrics, solder ball pitch and singulation quality all get claimed as part of the same package architecture. The dataset in scope covers 4,342 published records filed between 2015 and mid-2026, drawn from filings that reference board-level reliability, solder ball pitch, polymer dielectric, reconstituted wafer, line-space resolution or singulation defect alongside the core packaging terms.
Filing activity peaked in 2018 and has since settled into a lower but still active band; because publication trails filing by roughly 18 months, the last two years in any chart will look thinner than they will eventually turn out to be. The receiving-office mix is dominated by the United States, with meaningful secondary filing through the PCT route, Europe, Singapore, Taiwan and Germany — consistent with a technology that gets protected wherever assembly and test capacity sits.
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Filing trend and technology mix
Two views of the same 4,342 records: how filing volume has moved year over year, and how those records break down across IPC subclasses.
Filing trend, 2017–2026
Filings ran from 349 in 2017 to a peak of 411 in 2018, then eased to 286 by 2021 and 249 by 2024 — a 13% decline over that three-year window. 2025 and 2026 figures are still incomplete because of publication lag and should not be read as a drop-off.
Technology composition by IPC subclass
H01L (semiconductor devices) covers 90.4% of the 4,342 records, and H10W appears in 55.4% — together they frame WLCSP as primarily a device-and-interconnect discipline. Smaller shares in H05K (4.9%), H10D (3.5%), H01Q (2.4%), H10N (2.4%) and B81B (2.0%) mark adjacent claim territory in circuit assembly, antennas and MEMS integration. Because records can carry multiple classes, these shares sum to more than 100% and each is stated against the full 4,342-record base.
Shares are the percentage of the 4,342 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Wafer Level Chip Scale Packaging with Eureka
This page is one run against one query. Ask Eureka your own question about wafer level chip scale packaging and every answer comes back with the patent numbers behind it.
Try EurekaMost-cited records in the field
Methods and apparatus for controlling warpage in wafer level packaging processes
Filed by Applied Materials, this record addresses fine-pitch patterning by correcting substrate warpage in two stages around the polymer via-forming step, cycling the carrier or carrier-less substrate through controlled temperature holds before and after wafer level packaging processing.Abstract condensed from the original filing.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20100246152A1 | Integrated circuit chip using top post-passivation technology and bottom structure technology | 456 |
| 2 | US20130280826A1 | Adaptive patterning for panelized packaging | 378 |
| 3 | US20170062383A1 | Package Structures and Methods of Making the Same | 363 |
| 4 | US6396148B1 | Electroless metal connection structures and methods | 301 |
| 5 | US20150021754A1 | Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management | 294 |
| 6 | US20160093580A1 | Semiconductor device and method comprising redistribution layers | 285 |
| 7 | US20130200528A1 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP | 269 |
| 8 | US20160276307A1 | Semiconductor Device and Method of Forming POP Semiconductor Device with RDL Over Top Package | 267 |
| 9 | US20140015131A1 | Stacked fan-out semiconductor chip | 259 |
| 10 | US6846725B2 | Wafer-level package for micro-electro-mechanical systems | 255 |
Citation counts favour older filings simply because they have had longer to accumulate references — read them as a signal of influence within this corpus, not as a ranking of current importance.
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Browse MCP servers →What the numbers mean for filing strategy
Three patterns stand out once the ranking, trend and class data are read together.
The top of the field is dense, the rest is a long tail
Five companies account for 2,017 of the 4,342 records in scope, and the top ten extend that to 61.9%. That leaves roughly 38% of filing activity spread across the remaining ranked companies, which is where a new entrant is less likely to collide head-on with an incumbent's core claims.
Interconnect claims have become a track of their own
H10W's presence alongside the dominant H01L class signals that redistribution-layer and bump-interconnect claims are increasingly filed as a distinct sub-discipline rather than folded into general device claims, which matters when scoping a freedom-to-operate search.
A pullback from peak, not a retreat from the field
Filings fell from 286 in 2021 to 249 in 2024, continuing a gradual decline from the 2018 peak of 411. That is a normalisation after an earlier filing surge, not evidence the technology is being abandoned — 2025-2026 counts are still filling in under publication lag.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to wafer level chip scale packaging, with the prior art for and against each one.
Players and where activity is shifting
The ranking runs 100 companies deep, covering foundries, OSATs, IDMs and equipment suppliers rather than a single industry segment.
One company files far ahead of the field
The leading assignee holds 876 records against a fifth-place figure of 159 and a tenth-place figure of 106 — a steep drop-off that marks this as a field with one dominant filer surrounded by a much thinner second tier.
Recent-year activity has slowed across most leaders
Several of the most active historical filers show sharp year-on-year pullbacks in the latest year, including declines of 36% and 94% among leading assignees, and multiple leaders at zero latest-year filings. That pattern is consistent with publication lag rather than a wholesale exit from the space.
Co-filing is rare and concentrated
Only ten co-assignee pairs appear in the dataset, and the strongest of them links a packaging-equipment specialist with a named inventor at three joint records — a sign that most WLCSP patenting here happens inside a single corporate entity rather than through joint ventures.
| Assignee | Recent year | YoY |
|---|---|---|
| Qualcomm Inc | 7 | -36% |
| Taiwan Semiconductor Manufacturing Co Ltd (TSMC) | 3 | -94% |
| STATS ChipPAC Ltd | 0 | -100% |
| Samsung Electro-Mechanics Co Ltd | 0 | — |
| Samsung Electronics Co Ltd | 0 | -100% |
| Infineon Technologies AG | 0 | — |
| Intel Corp | 0 | -100% |
| Adeia Semiconductor Bonding Technologies Inc | 0 | -100% |
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, portfolio benchmarking or scouting.
Run a freedom-to-operate check on the leader's core claims
With one filer holding 876 of 4,342 records, any new WLCSP filing near redistribution-layer or fine-pitch claims should start with a targeted clearance search against that portfolio.
Explore the claims in Eureka →Track momentum, not just volume
Latest-year declines across several leading filers may reflect publication lag rather than real pullback; re-running the trend in a few quarters will sharpen that picture.
Set up monitoring in Eureka →Scope the under-claimed branches before they fill in
Antenna-in-package and MEMS-integrated WLCSP show thinner filing density than the core device classes, which is where an early, well-drafted claim has more room to stand.
Map white space in Eureka →Common questions about wafer level chip scale packaging patents
One company leads the ranked field with 876 records, well ahead of the fifth-ranked filer at 159 and the tenth-ranked filer at 106. The top five filers combined account for 46.5% of the 4,342 records in scope, and the top ten reach 61.9%. That leaves a substantial tail of smaller filers, so leadership at the top does not mean the whole field is closed off.
Filing peaked in 2018 at 411 records and has since eased, moving from 286 in 2021 to 249 in 2024, a 13% decline over that span. That is the most reliable read available because 2024 is the last year publication counts can be treated as complete; 2025 and 2026 figures are still filling in due to the typical 18-month lag between filing and publication, so they should not be read as evidence of a steeper drop.
H01L, the general semiconductor devices class, appears in 90.4% of the 4,342 records in scope, and H10W appears in 55.4%, indicating that redistribution-layer and interconnect claims are now filed as a substantial sub-track rather than an afterthought. Smaller but still notable shares sit in H05K (printed circuits, 4.9%), H10D (3.5%), H01Q (antennas, 2.4%), H10N (2.4%) and B81B (MEMS, 2.0%). Because a single record can carry several IPC classes, these percentages sum to more than 100% and are each measured against the same 4,342-record base.
The United States receives the largest share of filings at 3,265, followed by the WIPO PCT route at 290, Europe at 240, Singapore at 162, Taiwan at 113 and Germany at 57. That distribution tracks where wafer fabrication, assembly and test capacity is concentrated, and it is a reasonable guide to where enforcement risk and prior art density are both highest.
This Applied Materials filing claims a two-stage warpage-correction method that brackets the polymer via-forming step in wafer level packaging, using temperature holds and controlled cooling on a carrier or carrier-less substrate. Anyone developing a fine-pitch patterning process that manages warpage around that same process step should check whether their temperature-control sequence falls inside these claims. It is one representative record among many warpage-management filings in this dataset, so a full clearance check should look at the surrounding citation cluster, not this filing alone.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.