The Memory Wall Problem and Why IMC Has Become Urgent
In conventional computing architectures, data movement between compute and memory units consumes up to 62–80% of total system energy for data-intensive workloads. This is the von Neumann “memory wall” — a structural bottleneck that decades of CPU and GPU scaling have failed to resolve, and which deep neural network workloads have made intolerable.
In-memory computing (IMC) addresses this directly by performing computation within or adjacent to memory arrays, eliminating the energy-intensive round-trips between separate compute and memory dies. The field encompasses two principal paradigms: Computing-in-Memory (CIM), where arithmetic logic is embedded inside memory arrays such as SRAM, DRAM, ReRAM, or FeFET devices, and Processing-in-Memory / Near-Memory Computing (PIM/NMC), where logic dies are placed physically proximate to memory stacks via high-bandwidth interconnects.
The core computational primitive across nearly all filings in this patent landscape is matrix-vector multiplication (MVM) — the dominant operation in deep neural networks. In resistive memory arrays, MVM is executed by exploiting Ohm’s law and Kirchhoff’s current law. In SRAM-based designs, bit-serial and bit-parallel operations within the bitcell array perform equivalent multiply-accumulate (MAC) functions without moving data to a separate arithmetic unit.
This landscape is derived from a targeted set of patent and literature records spanning filings from 2000 through early 2026. It represents a snapshot of innovation signals within this dataset only and should not be interpreted as a comprehensive view of the full industry. All claims and statistics below are drawn exclusively from this dataset.
The urgency of IMC as a research and commercial priority is confirmed by the dataset’s filing trajectory: a foundational phase from 2000–2018, a scale-up phase from 2019–2023, and a maturation phase from 2024–2026 in which the most recent filings — dated as late as February 2026 — focus explicitly on chiplet-based IMC for large language model inference, signalling a decisive pivot from CNN/image-classification targets toward generative AI.
Four Architecture Clusters Defining the IMC Design Space
The in-memory computing patent landscape organises into four technically distinct clusters, each targeting a different memory substrate and application profile. Understanding the boundaries between clusters is essential for freedom-to-operate analysis and R&D positioning.
Cluster 1: Scalable Configurable CIM Core Arrays with On-Chip Networks
This is the most thoroughly patented cluster in the dataset, dominated by Princeton University with filings across six jurisdictions (WO, US, KR, CN, IN, JP, and TW). The architecture comprises an array of configurable in-memory computing units (CIMUs) interconnected by a programmable on-chip network. Each CIMU includes IMC hardware, ADCs/DACs, digital compute logic, and control registers. The architecture directly addresses the scale limitation of earlier single-macro CIM demonstrations — which were constrained to sub-128 Kb arrays — by tiling macros and routing dataflows across them. Princeton’s provisional filing dates to 2018, with PCT publication in August 2021.
Cluster 2: SRAM-Based Analog and Digital CIM Macros
Multiple Chinese university filings cover SRAM CIM macros targeting multi-bit weight storage and MAC operation efficiency. Key innovations include dual-port parallel weight reading (DPW) strategies, inter-core interconnect networks using near-memory scalable communication modules, multi-workload reconfigurability supporting arbitrary CPU-executable algorithms, and TCAM/LUT-based parallel multiply-accumulate execution. Assignees include Zhejiang University, South China University of Technology, and the University of Electronic Science and Technology of China, with filings concentrated between 2023 and 2025.
Cluster 3: DRAM-Based PIM and Near-Memory Computing
Samsung Electronics and academic groups have filed extensively on DRAM-integrated IMC modules. Samsung’s DRAM-bank-level IMC module embeds an ALU and result register within each DRAM bank, receiving operands from the row buffer or I/O module. Data placement methods optimise operand layout across DRAM banks to maximise IMC throughput. Additionally, 3D-stacked HBM systems with embedded logic layers and DIMM-based near-memory computing with cross-DIMM interconnect are represented in filings from Samsung (2021, 2024) and Peking University (2024).
Cluster 4: Non-Volatile Memory (NVM) CIM — FeFET and ReRAM
This cluster exploits the multi-level analog storage characteristics of non-volatile memory devices to embed multi-bit weights directly in memory cells, eliminating SRAM’s large cell area and static power overhead. FeFET-based designs achieve 4-bit/8-bit weight storage with integrated shift-add operations. Resistive memory crossbar arrays perform vector-matrix multiplication via Ohm’s law, with bit-line circuits implementing threshold comparison and inner-product accumulation. Zhejiang University’s 2024 FeFET-based CIM filing represents the maturation frontier of this cluster.
In-memory computing SRAM-based analog CIM is the dominant technical substrate for edge AI inference in this patent dataset, followed by DRAM-based PIM for datacenter and HPC workloads, and an emerging cluster of non-volatile memory CIM using FeFET and ReRAM devices.
Explore the full in-memory computing patent landscape, including claim-level analysis and assignee maps, in PatSnap Eureka.
Explore IMC Patents in PatSnap Eureka →Patent Landscape: Who Holds the Power Positions
The geographic and assignee distribution of IMC patents in this dataset reveals a tripartite structure: a US academic institution with a blocking-level patent family, a single vertically integrated memory manufacturer, and a dense cluster of Chinese academic institutions generating high-volume but narrower filings.
The Trustees of Princeton University holds the dominant patent family in scalable configurable CIM core array architecture, with filings in WO, US, KR, CN, JP, IN, and TW — the widest geographic footprint of any single IMC assignee in this dataset. The foundational provisional was filed in 2018 (US provisional 62/686,296), with PCT publication in August 2021 and national phase entries continuing through 2025. Any product team building tiled CIM accelerators for AI inference should conduct a freedom-to-operate analysis against this family, according to WIPO filing records, before committing to silicon.
Princeton University’s scalable CIM array patent family spans seven jurisdictions — WO, US, KR, CN, JP, IN, and TW — making it the widest geographic IMC patent position held by any single assignee in this dataset, with filings active from 2018 through 2025.
Samsung Electronics is the only vertically integrated memory manufacturer with active DRAM-level IMC architecture filings visible in this dataset. Samsung’s DRAM-bank-level IMC module and data placement patents, filed in KR and JP between 2021 and 2024, give Samsung a potential first-mover advantage in commercialising PIM-DRAM as a drop-in upgrade for existing server memory slots — a path with far lower system integration barriers than custom CIM ASICs. Samsung’s High Bandwidth Memory (HBM) PIM systems are also represented in the dataset.
China is the most active jurisdiction for core IMC architecture filings, with at least 15 relevant patents from Chinese academic institutions — including Zhejiang University, Shanghai Jiao Tong University, South China University of Technology, Tsinghua University, Peking University, Beihang University, National University of Defense Technology, and the University of Electronic Science and Technology of China — and companies including Beijing Pinxin Technology and Shenzhen Huaxin Xing Semiconductor. The majority are university-origin patents filed between 2022 and 2026, indicating strong government-backed academic research pipelines, consistent with patterns tracked by OECD innovation policy analysis.
“Chinese academic institutions are generating high volumes of narrow-scope IMC patents, particularly in SRAM macro design, toolchain development, and NVM devices — building a deep defensive patent thicket in implementation-level IMC IP that could constrain foreign vendors seeking to manufacture or sell in the Chinese market.”
IBM holds legacy compute architecture patents addressing NUMA architectures and has recently re-entered the CIM space with a 2D mesh CIM accelerator architecture filing for DNN workloads (JP, 2025). Google LLC filed on 3D-DRAM chiplets for LLM serving in KR (2024). Intel Corporation and Alibaba Group hold related PIM and memory-access-cost reduction patents in this dataset but are not among the primary IMC architecture assignees. University of Southern California (Prometheus heterogeneous PIM architecture, 2019) and University of Michigan (memory processing unit, 2021) hold US-active patents in the NVM/PIM cluster.
The LLM Pivot: How Generative AI Is Redefining IMC Targets
LLM inference is memory-bandwidth-bound, not compute-bound — a fundamental difference from CNN workloads that makes near-storage and near-memory execution economically attractive even at modest compute density. This architectural insight is driving the most significant reorientation in IMC design targets since the field’s inception.
Architectures optimised for 2017-era CNN workloads — designed around small weight matrices and fixed-point 8-bit arithmetic — are structurally mismatched to LLM requirements, which involve very large weight matrices, mixed-precision operations, and memory-bandwidth dominance. The dataset’s 2024–2026 filings reflect this mismatch being actively resolved by multiple independent research groups.
Tsinghua University’s 2025 edge LLM inference system uses NAND Flash and DRAM chiplet stacks with near-storage compute for prefill and decode phases, while Google LLC’s 2024 3D-DRAM chiplet system targets LLM serving with low-power, bandwidth-optimised compute-memory chiplets — both explicitly addressing the memory-bandwidth-bound nature of LLM inference.
Three organisations have filed the most technically specific LLM-targeted IMC patents in this dataset. Tsinghua University (CN, 2025) filed on an edge-side LLM inference system using NAND Flash and DRAM chiplet stacks with near-storage compute, targeting the prefill and decode phases separately. Google LLC (KR, 2024) filed on serving large language models using 3D-DRAM chiplets, optimising for low-power, bandwidth-optimised compute-memory integration. Shanghai Jiao Tong University (CN, 2026) filed the most recent patent in this dataset: a heterogeneous chiplet architecture simulation and search method for LLM inference, integrating PIM/CIM chiplets with systolic arrays under mixed parallel strategies — tensor, pipeline, data, and expert parallelism — co-optimised via simulated annealing with Pareto-frontier optimisation.
This pivot also extends to combinatorial optimisation: the National University of Defense Technology of China filed in 2025 on DRAM-based globally connected Ising architecture compute systems, representing an expansion of IMC beyond neural networks toward physics-inspired computing for combinatorial optimisation problems. Standards bodies including IEEE have begun formalising memory interface standards that will shape how these architectures integrate with host systems.
Five Emerging Vectors Shaping IMC Through 2026
The 2024–2026 filings in this dataset signal five distinct innovation vectors that together define the frontier of in-memory computing architecture research and indicate where commercial development pressure is building.
1. LLM-Optimised Memory-Compute Stacks
Both Tsinghua University (NAND Flash + DRAM hybrid stacks) and Google (3D-DRAM chiplets) filed in 2024–2025 explicitly targeting LLM serving. The shared architectural insight is that LLM inference is memory-bandwidth-bound, making near-storage and near-memory execution economically attractive even at modest compute density.
2. FeFET and Non-Volatile CIM
Zhejiang University’s 2024 FeFET-based CIM filing represents a maturation of NVM-CIM beyond SRAM, achieving non-volatility and multi-bit analog storage in a single device. This direction eliminates the SRAM-to-accelerator weight loading overhead that limits real-time adaptation in deployed inference systems.
3. IMC Compilation and Simulation Toolchains
Beihang University (Beijing University of Aeronautics and Astronautics) filed in 2025 a digital CIM architecture compilation and simulation toolchain targeting DNN-to-IMC mapping, performance profiling, and instruction optimisation. This signals that IMC is transitioning from a device-level to a system-level design challenge requiring dedicated software infrastructure — a maturation milestone comparable to the emergence of GPU compiler stacks.
Multiple filings — Beihang University’s toolchain, Shanghai Jiao Tong University’s chiplet search system, and South China University of Technology’s multi-workload architecture — explicitly address the absence of compilers, simulators, and mapping algorithms for IMC. R&D teams entering this space should treat the software stack as an equal investment priority alongside silicon architecture.
4. Chiplet Heterogeneous Architecture Search for AI
Shanghai Jiao Tong University’s 2026 filing on heterogeneous chiplet architecture simulation and search integrates PIM/CIM chiplets with systolic arrays under mixed parallel strategies, co-optimised via simulated annealing with Pareto-frontier optimisation — pointing toward automated IMC system design where architecture selection is itself a computational problem.
5. Unified Memory-Storage Semantic Architectures
Shenzhen Huaxin Xing Semiconductor’s 2025 patent on an intelligent unified memory-storage architecture uses Compute Express Link (CXL)-based semantics, embedded compute engines within SSDs, and intelligent tiering and placement — extending IMC principles into the persistent storage tier and aligning with emerging CXL ecosystem standards being developed through bodies such as JEDEC.
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Monitor IMC Patents in PatSnap Eureka →Strategic Implications for R&D and IP Teams
The patent landscape described above has direct, actionable implications for semiconductor teams, IP counsel, and investors evaluating positions in the in-memory computing space. Five strategic conclusions emerge from the dataset.
Freedom-to-operate risk around Princeton’s patent family is real and multi-jurisdictional. Princeton’s scalable configurable CIM core array architecture claims cover WO, US, KR, CN, JP, IN, and TW. Product teams building tiled CIM accelerators for AI inference must conduct FTO analysis against this family before committing to silicon. The family’s breadth — spanning the architecture of CIMUs, on-chip networks, ADC/DAC integration, and control registers — means that design-around options require early engagement.
Samsung’s PIM-DRAM position has a lower commercialisation barrier than custom CIM ASICs. As the only vertically integrated memory manufacturer with active DRAM-level IMC IP in this dataset, Samsung can offer PIM-DRAM as a drop-in upgrade for existing server memory slots. This path avoids the system integration complexity of custom CIM ASICs and could accelerate enterprise adoption. Competing memory manufacturers should assess whether their own DRAM roadmaps include IMC capability.
China’s defensive patent thicket is a market access consideration. At least 15 Chinese academic IMC patents in this dataset, filed between 2022 and 2026, collectively cover SRAM macro design, toolchain development, NVM devices, and near-memory interconnects. While individually narrower than Princeton’s family, this output could constrain foreign vendors seeking to manufacture or sell IMC products in the Chinese market. IP strategy for China market entry should account for this thicket, consistent with patent landscaping practices recommended by EPO.
LLM inference is the dominant design target through 2026 and beyond. R&D teams should re-baseline architecture tradeoffs against transformer attention and feedforward layer shapes — very large weight matrices, mixed-precision arithmetic, and memory-bandwidth dominance — rather than the CNN workload profiles that drove most pre-2023 IMC design decisions.
The software stack is the primary commercialisation barrier. Beihang University’s toolchain filing and Shanghai Jiao Tong University’s chiplet search system both reflect an industry-wide recognition that IMC cannot reach production without compilers, simulators, and mapping algorithms. Teams entering this space should treat the software stack as an equal investment priority alongside silicon architecture. This mirrors the trajectory of GPU computing, where software ecosystem investment (CUDA, ROCm) proved as commercially decisive as hardware performance.
The software-hardware co-design gap is the primary commercialisation barrier for in-memory computing architecture in 2026, with multiple filings from Beihang University and Shanghai Jiao Tong University explicitly addressing the absence of compilers, simulators, and DNN-to-IMC mapping algorithms.