LPP Source Architecture: The 100-Meter Laser Path Behind Every EUV Pulse
Every ASML EUV scanner begins with a laser-produced plasma (LPP) source in which high-power CO₂ laser pulses irradiate tin (Sn) droplets to generate 13.5 nm EUV-emitting plasma. ASML’s incumbent LPP source relies on a continuous-discharge CO₂ laser MOPA (master oscillator and power amplifiers) structure developed by Cymer, operating at a repetition frequency approaching 100 kHz. The amplifiers operate at low gas pressure of approximately 0.1 atm, producing a low gain coefficient of approximately 0.004 cm⁻¹ — a physical constraint that forces a multi-stage amplification chain stretching the laser path to over 100 meters, which is one of the root causes of the scanner’s extraordinarily large physical footprint.
Each tin droplet requires approximately 250 mJ of pulse energy and 15 MW of pulse power to generate sufficient EUV-emitting plasma. This extreme power requirement is what drives the enormous physical complexity of the ASML source subsystem. To improve on this architecture, alternative approaches combine a high-repetition-rate TEA CO₂ laser with a pre-pump picosecond laser: the picosecond pulse first converts liquid tin droplets into a fine mist sphere, which is then irradiated by the main pulse to form the high-temperature plasma emitting 13.5 nm EUV light. Notably, the same patent architecture can be reconfigured with gadolinium (Gd) targets to produce 6.7 nm EUV radiation — pointing toward a next generation of even shorter-wavelength sources that could deliver approximately another 2× resolution improvement beyond the current High-NA generation.
ASML’s LPP EUV light source operates at a repetition frequency approaching 100 kHz and requires approximately 250 mJ of pulse energy and 15 MW of pulse power per tin droplet to generate 13.5 nm EUV-emitting plasma. The multi-stage CO₂ MOPA amplification chain stretches the laser path to over 100 meters.
Precise energy control is critical to pattern fidelity. An ASML Netherlands B.V. 2019 patent discloses a lithography system in which a sensing system provides real-time signals representing the spatial intensity distribution of EUV radiation. A control system uses these signals to determine the far-field intensity distribution and generates closed-loop control signals that adjust both the illumination and the EUV source generation simultaneously — enabling rapid detection and correction of asymmetries in the illumination field. Complementing this, TSMC’s 2023 patent on 3D characterization acquires both the laser beam profile and the EUV energy distribution in three-dimensional mode, performs a joint analysis of these datasets, and feeds the results back to the radiation source actuators. This real-time 3D characterization is essential for maintaining the source stability needed for sub-2nm patterning, where any dose variation directly translates to critical dimension (CD) error.
“The CO₂ MOPA system already operates at or near its design limits for pulse power and repetition rate, making incremental power scaling at 13.5 nm extremely difficult — and pointing the industry toward gadolinium-target 6.7 nm sources as the next resolution lever.”
From NA 0.33 to 0.55: How the High-NA Optical Engine Halves the Half-Pitch
The resolution limit of any lithographic system is governed by the Rayleigh criterion — R = k₁ × λ / NA — and increasing the numerical aperture is the most direct lever for improving resolution at a fixed wavelength. Moving from NA = 0.33 on the conventional NXE platform to NA = 0.55 on the High-NA EXE:5000 platform reduces the theoretical half-pitch resolution from approximately 13 nm to approximately 8 nm at 13.5 nm wavelength, enabling single-exposure patterning of logic features at the 2nm node and below. Achieving NA = 0.55 requires fundamentally redesigned projection optics, because essentially all materials absorb 13.5 nm radiation strongly — precluding any refractive lens elements and demanding an all-reflective optical train.
Carl Zeiss SMT, ASML’s exclusive optics partner, has developed the mirror systems that make High-NA EUV possible. The illumination optics for EUV systems use a two-stage faceted mirror architecture: a field facet mirror followed by a pupil facet mirror. Carl Zeiss SMT GmbH’s 2018 patent describes a field facet mirror in which individual field facets have curved reflection surfaces whose curvature can be dynamically adjusted, and each field facet is assigned to multiple pupil facets on the pupil facet mirror. This flexible assignment enables control of the effective illumination pupil — a prerequisite for off-axis illumination modes (dipole, quadrupole, annular) that are essential for resolving dense line/space patterns near the 2nm node. Earlier Carl Zeiss SMT AG work on folding geometries establishes the chief ray geometry and anti-parallel ray arrangement that keeps the optical path compact, which is directly relevant to the more extreme folding required in High-NA architectures.
The High-NA EXE:5000 uses a 26×16.5 mm exposure slit, compared to 26×33 mm for the NXE platform. The slit area is reduced to accommodate the larger numerical aperture without requiring prohibitively large mirrors. This makes dose uniformity across the reduced field even more critical than on the conventional platform.
The EUV light source generates a sequence of light pulses at a defined repetition frequency, and at least one optical modulation component within the illumination system is modulated in synchronisation with that frequency to improve illumination field homogeneity — as disclosed in a Carl Zeiss SMT AG 2010 illumination system patent. For High-NA, where the reduced exposure slit means fewer pulses contribute to each point on the wafer, this synchronised modulation becomes even more important for controlling dose uniformity. According to the WIPO patent database, the volume of EUV optics-related filings has grown substantially since 2018, reflecting the industry’s acceleration toward the High-NA generation.
Explore the full patent landscape for High-NA EUV optical systems in PatSnap Eureka.
Search EUV Patents in PatSnap Eureka →Mask Engineering at High-NA: Shadowing, Phase Shifts, and Sub-Resolution Gratings
At High-NA, the illumination angle at the mask increases significantly, exacerbating mask shadowing effects — where the finite thickness of the absorber layer on the EUV mask creates geometric shadows that distort the printed pattern. Because EUV optics are non-telecentric (the beam strikes the mask at approximately 6 degrees from normal), absorber thickness directly translates to pattern placement error. Managing these effects at the 2nm node requires both absorber engineering and advanced mask layout strategies. Two patent disclosures from 2025 — one from IMEC and one from ASML — define the current state of the art.
ASML’s 2025 half-pitch shift mask (HPSM) patent discloses that a dark-line width of 56 nm on the mask produces a printed critical dimension (CD) on the substrate as small as 14 nm — a 4× reduction factor. The patent also introduces a waveguide-based structure within the mask to compensate for CD variation as a function of pattern pitch, a critical requirement at the sub-2nm logic node.
IMEC’s 2025 pending patent on sub-resolution gratings in EUV imaging describes a mask design methodology specifically for high- and ultra-NA EUV lithography. The mask includes a pattern derived from the superposition of two sub-layouts: the first contains the main features to be printed, while the second contains sub-resolution gratings whose lines extend perpendicular to the main feature direction and are designed to be non-printable at high or ultra-NA conditions. These sub-resolution gratings optimise imaging conditions including best focus, maximum contrast, and depth of focus, thereby improving the overall lithographic process window at the dimensions required for 2nm logic.
The absorber layer on EUV masks must satisfy demanding reflectivity specifications. The EUV mask structure consists of alternating Mo/Si multilayer reflective stacks topped by an absorber layer. Maintaining absorber EUV reflectivity in the 5–15% range while keeping the surrounding EUV absorption region below 1% is critical for achieving the image contrast needed at advanced nodes. At High-NA, because shadowing from even thin absorbers worsens, there is strong industry pressure to move to low-n absorbers that allow thinner films while maintaining sufficient EUV absorption — an ongoing area of mask materials development tracked by standards bodies including SEMI.
Pellicle membranes that protect the mask from contaminating particles are another component where ASML holds deep IP. A 2022 ASML pellicle patent discloses a membrane stack with a base layer comprising a compound of a metal with Si, B, C, or N, sandwiched between two metallic oxide cover layers of differing compositions. This layered architecture balances EUV transmission, mechanical robustness, and thermal stability — all of which become more challenging at High-NA due to higher EUV dose requirements and the reduced exposure slit area.
ASML’s 2025 half-pitch shift mask patent demonstrates that a 56 nm dark-line width on the mask produces a printed critical dimension of just 14 nm on the substrate — a 4× reduction. A new waveguide-based mask structure compensates for the CD variation that occurs as a function of pattern pitch, which is a critical requirement at the sub-2nm node where pitch variation tolerance is extremely tight.
Computational Lithography and Overlay Control: Closing the Process Window at 2nm
At the 2nm logic node, computational lithography — particularly source-mask optimisation (SMO) — becomes indispensable for achieving acceptable process windows, because the physical process window is insufficient for manufacturing yield without software-driven co-optimisation. SMO simultaneously optimises source shape and mask main features plus sub-resolution assist features (SRAFs) using a conjugate gradient method, with the objective function combining imaging fidelity with source and mask penalty terms. The method compensates for EUV-specific effects including optical proximity effects, stray light (flare), resist effects, and mask shadowing effects — all of which are aggravated at High-NA due to the increased illumination angle and higher sensitivity of the resist to dose variations.
Source-mask optimisation (SMO) for EUV lithography simultaneously optimises source shape, mask main features, and sub-resolution assist features (SRAFs) to compensate for optical proximity effects, stray light, resist effects, and mask shadowing. Without SMO, the process window at sub-2nm dimensions is insufficient for manufacturing yield. This approach is documented in a 2015 Beijing Institute of Technology patent and extended to include design rule co-optimisation in a 2016 Chinese Academy of Sciences patent.
An extension of the SMO framework includes chip design rule optimisation as a co-optimisation variable: by fine-tuning feature widths and spacings within the design rules, the overall process window can be enlarged without changing device dimensions, reducing the need for aggressive mask corrections. This design-technology co-optimisation (DTCO) approach is expected to be a standard part of the 2nm and beyond process flow. TSMC’s 2025 patent on lithography process selection describes a semiconductor processing system that analyses layout features and automatically routes them to either an EUV system or a 193i immersion system based on feature dimensions — a practical implementation of DTCO at the process level, directing the smallest and most critical features to the High-NA EUV scanner while keeping cost-scalable layers on legacy tools.
Overlay errors — the misregistration between successive patterned layers — are one of the dominant yield limiters at the 2nm node. Samsung Electronics has developed critical methods for controlling overlay errors. A 2021 Samsung patent discloses a system in which a first overlay parameter is corrected through its correlation with a second overlay parameter, enabling the control unit to compensate for mirror-induced distortions in the projection optics system. Since EUV projection systems use six or more aspheric mirrors, thermally induced mirror shape changes directly generate overlay errors. Samsung’s 2024 patent describes using laser heating of specific mirrors to allow active correction by thermally deforming individual projection mirrors to counteract systematic overlay deviations. Research published through IMEC has further characterised the relationship between mirror thermal states and overlay budgets at the High-NA node.
“Samsung’s active mirror thermal control — using laser heating to deliberately deform individual projection mirrors — represents a shift from passive overlay correction to a closed-loop hardware-software system that treats the optical train as a reconfigurable element.”
For illumination system optimisation, Samsung also discloses a method that uses linear programming to assign pupil facet mirror positions to a target illumination source map, subject to a symmetry criterion. The algorithm assigns priorities to facet positions according to the target image and converts the optimised mirror assignment into a form directly executable by an EUV scanner — a closed-loop digital workflow connecting computational lithography with hardware configuration. This approach aligns with the broader trend in semiconductor manufacturing toward digitally orchestrated process control, as documented by SIA roadmap analyses.
Analyse Samsung, TSMC, and ASML overlay correction patents side-by-side in PatSnap Eureka.
Explore Overlay Control IP in PatSnap Eureka →IP Landscape: Who Owns the Enabling Stack for Sub-2nm Patterning
The patent data reveals a clear stratification of innovation roles across the High-NA EUV enabling stack, with each key player occupying a distinct and largely non-overlapping IP territory. ASML Netherlands B.V. is the sole manufacturer of High-NA EUV scanners (the EXE:5000 series) and holds foundational IP in EUV source control, pellicle design, and mask technology. Carl Zeiss SMT — as ASML’s exclusive projection optics supplier — owns the mirror system and illumination architecture IP that underpins both the NXE and EXE platforms. Samsung Electronics leads among semiconductor manufacturers in scanner control, overlay correction, and illumination optimisation IP, with active patents spanning 2020 through 2026. TSMC is active in EUV source characterisation and process selection automation. IMEC occupies the academic-consortium role in High-NA mask design innovation. Chinese institutions are most active in LPP source alternatives, SMO algorithms, and mask inspection.
The patent dataset surveyed encompasses approximately 30 records spanning EUV light source systems, illumination optics, mask design, overlay correction, and computational source-mask optimisation. The dominant assignees include ASML Netherlands B.V., Carl Zeiss SMT (AG and GmbH), Samsung Electronics, TSMC, IMEC, and several Chinese research institutions including the Chinese Academy of Sciences and Beijing Institute of Technology. The primary technical approaches cluster around four areas: LPP EUV source engineering for higher power and shorter wavelengths; high-numerical-aperture projection optics with faceted mirror systems; advanced mask designs including half-pitch shift masks and sub-resolution assist features; and source-mask joint optimisation (SMO) computational methods.
Chinese institutions’ focus on indigenous LPP source alternatives and SMO algorithms reflects China’s strategic push to develop EUV capabilities outside the ASML ecosystem — a trend that the WIPO global patent filings data increasingly reflects. The gadolinium-target 6.7 nm source architecture documented in the 2025 Chinese Academy of Sciences patent represents the most technically ambitious element of this effort, targeting a wavelength that could deliver approximately another 2× resolution improvement beyond the current High-NA EUV generation. Whether indigenous manufacturing infrastructure can be assembled to support such a source remains an open question tracked closely by semiconductor analysts and policymakers at organisations such as the SIA and OECD.
Gadolinium (Gd) targets in a laser-produced plasma EUV source can generate 6.7 nm EUV radiation, which represents approximately a 2× resolution improvement over the 13.5 nm wavelength used in current ASML High-NA EUV systems. This next-generation source architecture is documented in a 2025 patent from the Chinese Academy of Sciences Space Information Innovation Research Institute.
For IP professionals and R&D leaders monitoring the sub-2nm patterning landscape, the patent record makes clear that no single organisation owns the full enabling stack. The system-level capability emerges from ASML’s integration of Carl Zeiss optics, Cymer source technology, and an ecosystem of computational and mask innovations from chipmakers and research consortia. Tracking the evolution of this distributed IP landscape — particularly the emerging Chinese filings on alternative source architectures and the IMEC-led mask innovation for ultra-NA — is essential for anticipating where the next capability gaps and licensing dependencies will emerge. PatSnap’s innovation intelligence platform at patsnap.com/products/patent-analytics provides the tools to map these dependencies at the claim level, while patsnap.com/products/eureka enables AI-assisted analysis of the full EUV patent corpus.