Reducing etch loading effects in HAR DRAM capacitors

What etch loading is and why it matters in HAR DRAM capacitor fabrication

Etch loading is the variation in etch rate and etch depth across a wafer or die caused by pattern density differences. In DRAM arrays, extremely dense capacitor hole patterns generate high polymer loading and local gas depletion conditions that reduce local etch rates relative to isolated peripheral structures — creating non-uniform contact depths that degrade yield and introduce junction leakage.

The challenge is structural: as DRAM technology scales, capacitor holes must be etched deeper to maintain capacitance, while the hole diameter shrinks. Aspect ratios exceeding 50:1 are common in leading-edge nodes, according to IEEE process integration literature. At these depths, the plasma chemistry inside the hole differs substantially from the bulk gas phase above the wafer surface, and any variation in local pattern density amplifies this difference. The result is that capacitor contacts in the dense array region etch more slowly than those in the peripheral circuit region, and if the etch is extended to clear the array contacts, the peripheral contacts over-etch into underlying diffusion regions — causing junction leakage and device failure.

The dataset analysed for this article spans approximately 60 patents and related records across jurisdictions including Korea, Japan, China, and Taiwan, filed between the early 1990s and 2024. Key assignees include Samsung Electronics, NEC Corporation, Sony Corporation, Fujitsu, IBM, Infineon Technologies, Applied Materials, and Tokyo Electron. Four dominant technical themes emerge: etch stopper layer deployment, CMP-assisted planarization, structural modifications such as dummy patterns and reinforced storage nodes, and emerging single-HAR-etch 3D DRAM strategies.

Etch stopper layer architectures: the industry-validated baseline

The most broadly adopted approach to preventing over-etch in HAR DRAM capacitor contacts is the deliberate insertion of dual etch stopper layers at critical interfaces. A first stopper layer covers peripheral MOS transistors while a second is positioned above the capacitor sections of DRAM memory cells — ensuring that even when etch rate variation leads to different etch depths across the wafer, each stopper provides a reliable endpoint for its respective region.

This dual-stopper architecture was independently developed and claimed by multiple organisations. Fujitsu’s 2001 patent on LSI devices co-integrating DRAM cells and logic describes exactly this configuration: a first etching stopper layer covering peripheral MOS transistors and a second stopper above the DRAM capacitor sections, preventing over-etching into impurity diffusion layers or element isolating films. Sony Corporation filed an independent patent in the same year describing the identical two-stopper approach for suppressing junction leaks by controlling etch depth in the presence of aspect-ratio-dependent loading effects. Fujitsu revisited and reaffirmed the same architecture in a 2013 patent, confirming its continued relevance to mixed DRAM-logic LSI structures with large-aspect-ratio contacts.

“The consistency of the dual-stopper solution across independent assignees — Fujitsu and Sony Corporation both filing in 2001 — confirms its status as an industry-validated technique for controlling etch depth in high-aspect-ratio DRAM capacitor contacts.”

The physical mechanism these layers exploit is etch selectivity. Silicon nitride stopper layers are used against oxide-based interlayer dielectrics, exploiting the high selectivity of fluorine-based plasma chemistries toward SiO₂ over Si₃N₄. By positioning nitride stops at the level of the capacitor node or transistor diffusion region, the process window for contact etch becomes tolerant to the etch rate non-uniformity intrinsic to HAR loading effects. This selectivity mechanism is well-characterised in the plasma etch literature published by The Electrochemical Society.

CMP planarization as a pre-etch uniformity tool

CMP planarization reduces etch loading by eliminating the topographical variation that amplifies loading effects before the capacitor contact etch begins. United Microelectronics Corporation’s 1998 patents established the core process flow: deposit a conformal silicon nitride etch-stop layer over the entire device structure including exposed source/drain regions, deposit a thick oxide layer, perform CMP to planarize the oxide surface, then etch capacitor contact openings through the planarized oxide, stopping reliably on the nitride layer.

This approach decouples etch loading sensitivity from underlying topography. Because a flat oxide surface presents a uniform etch front to the plasma across the entire die, the variation in etch depth between dense-array and peripheral regions is substantially reduced. A second UMC patent from the same year adds a two-step etch refinement: the primary contact etch stops on the nitride layer, then a selective isotropic etch removes the nitride within the opening before forming the capacitor electrode in contact with the exposed source/drain region. This two-step process further reduces loading sensitivity by limiting the HAR phase of the etch to a uniform oxide film of known, CMP-controlled thickness.

Planarization also manages step height differences at the boundary between DRAM and logic sections in embedded DRAM processes. Renesas Technology’s 2005 manufacturing method describes etching the first interlayer dielectric in the DRAM section by a depth corresponding to the cell plate electrode thickness, then using CMP to co-planarize both the DRAM and logic sections after conductor film deposition. This prevents loading-induced step-height differences at the DRAM/logic boundary from propagating into subsequent lithography and etch steps — a concern well-documented in process integration literature from SEMATECH.

Structural innovations: dummy patterns, poly spacers, and electrode engineering

Structural modifications to the capacitor architecture and surrounding layout can substantially reduce etch loading without requiring changes to the plasma chemistry itself. Three distinct structural approaches are documented in the patent dataset: dummy pattern insertion to homogenise effective pattern density, poly spacer reinforcement to prevent storage node collapse after aggressive HAR etching, and multilayer electrode engineering to resist post-etch chemical attack.

Dummy pattern insertion

Dummy structures are non-functional etch targets inserted in low-density areas of the mask to homogenise the effective pattern density seen by the plasma, reducing etch rate and depth variation between dense-array and isolated peripheral regions. The structural principle is demonstrated by KAIST’s 2023 patent on dummy TSV structures in semiconductor chips, where dummy elements placed between signal and ground through-silicon vias reduce leakage current and implicitly improve the uniformity of the etch environment around high-aspect-ratio features.

Storage node collapse prevention

Storage node collapse is a mechanical consequence of aggressive HAR capacitor etching, occurring during the wet clean steps that follow HAR dry etching. Samsung Electronics’ 2007 DRAM capacitor manufacturing method addresses this by introducing poly spacers on both sidewalls of the storage node and using a material layer with etch selectivity as a sacrificial support. This structural approach prevents mechanical failure during wet clean and effectively extends the process window for deep capacitor etches without needing to reduce the aspect ratio — a critical yield-enabling technique at advanced DRAM nodes.

TiON/TiN multilayer electrode engineering

Tokyo Electron’s 2019 patent addresses the challenge of post-etch chemical attack during wet processes by engineering a five-layer TiON/TiN laminate lower electrode structure. The outer TiON layers with lower oxygen concentration provide hydrofluoric acid resistance, while the inner TiON and TiN layers control stress — reducing the tendency for electrode deformation after the HAR etch release step. This materials engineering approach compensates for post-etch stress and chemical attack without altering the HAR etch process itself, and is consistent with electrode materials research published by Nature on transition metal nitride thin films.

Single-HAR-etch 3D DRAM: eliminating the loading problem at source

Applied Materials’ 2022 and 2024 patents represent the most disruptive long-term solution to etch loading: a 3D DRAM architecture in which a single HAR etch of a grid pattern of holes into a substrate with alternating crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) layers provides chemistry access for all subsequent lateral etching and deposition steps — without requiring additional HAR etching steps.

The substrate is formed by heteroepitaxial deposition of alternating c-Si and c-SiGe layers. The single HAR etch creates a grid of holes whose geometry is configured to allow lateral etch chemistry to selectively remove the c-SiGe layers, forming the three-dimensional capacitor and transistor structures of the DRAM cell. Because all subsequent patterning is lateral — not vertical — the repeated loading-sensitive HAR etch steps that accumulate process variation in conventional DRAM fabrication are fundamentally eliminated. The 2024 patent from Applied Materials confirms continued investment in this process paradigm, indicating it is progressing toward manufacturability.

“Applied Materials’ single-HAR-etch 3D DRAM architecture eliminates repeated loading-sensitive deep-etch steps altogether by forming all 3D DRAM features through lateral access from a single hole pattern — a structural paradigm shift away from iterative deep etching.”

The significance of this approach extends beyond etch loading control. By reducing the number of HAR etch steps from multiple (in conventional stacked or trench DRAM) to one, the architecture also reduces cycle time, etch tool utilisation, and the cumulative process variation budget. This is consistent with the direction of 3D integration described in roadmap documents from the Semiconductor Industry Association.

Assignee landscape and innovation trends across the patent dataset

The patent dataset reveals a concentration of DRAM etch-related innovation among a relatively small group of major semiconductor companies, with notable regional and technical clustering across the approximately 60 patents analysed.

Samsung Electronics appears across multiple patents spanning trench isolation, recess channel array transistors, and storage node collapse prevention (2006, 2007). Samsung’s contributions reflect a systems-level approach combining HAR etch process control with structural reinforcement of storage nodes — addressing both the etch loading event and its mechanical consequences.

Fujitsu and Sony Corporation are prominent in the etch stopper layer architecture space, with both companies filing independently on dual-stopper layer approaches for DRAM-logic mixed integration in 2001. Fujitsu reaffirmed this architecture in a 2013 patent, demonstrating its longevity as a process solution.

United Microelectronics Corporation leads in CMP-assisted planarization for DRAM capacitor contact etching, with two closely related patents from 1998 that define the silicon nitride stop layer plus oxide CMP framework still referenced in modern process flows.

Applied Materials represents the most recent innovation frontier, with its 2022–2024 patents on single-HAR-etch 3D DRAM process flows representing a structural paradigm shift away from iterative deep etching toward lateral processing after a single high-aspect-ratio hole formation.

IBM contributed foundational work on vertical DRAM structures incorporating nitride STI liners (2005, 2010), demonstrating how liner material selection adjacent to HAR structures can modulate etch selectivity and dopant redistribution simultaneously. Tokyo Electron (2019) represents the materials engineering perspective, showing that lower electrode composition engineering through TiON/TiN multilayer stacks can compensate for post-etch stress and chemical attack without altering the HAR etch process itself. Process equipment and materials standards relevant to these approaches are maintained by SEMI.