The Physical Link Between D_it and V_TH Instability in GaN MIS-HEMTs
Interface trap density (D_it) at the gate dielectric/GaN boundary is the primary physical parameter governing the magnitude and direction of threshold voltage (V_TH) instability in GaN metal-insulator-semiconductor HEMTs (MIS-HEMTs). Trap states at this boundary capture or emit charge carriers under varying gate bias conditions, modulating the effective charge in the channel and shifting the electrostatic condition at which the two-dimensional electron gas (2DEG) is formed. Reported D_it values at nitride/GaN interfaces span a remarkably wide range — from approximately 2×10¹⁰ cm⁻² eV⁻¹ to above 3×10¹³ cm⁻² — and this range directly maps onto the severity of V_TH drift observed in power switching applications, as documented across more than 50 sources spanning 2013–2025.
The Slovak Academy of Sciences’ comprehensive 2020 review of bias-temperature instabilities (BTI) in both depletion- and enhancement-mode GaN MIS-HEMTs established that both the density and energetic distribution of interface traps are critical parameters — not just their total count. Under positive gate stress, interface traps at the dielectric/GaN boundary capture electrons, producing a positive V_TH shift as the trapped negative charge partially depletes the 2DEG. Under negative gate bias, previously filled traps emit electrons, causing the opposite V_TH drift. This bidirectional behaviour is what makes interface-trap-driven instability particularly challenging for power converter design, where gate voltages swing between positive and negative values during every switching cycle.
Interface trap density (D_it) at the gate dielectric/GaN boundary in GaN MIS-HEMTs ranges from approximately 2×10¹⁰ cm⁻² eV⁻¹ to above 3×10¹³ cm⁻², and this parameter is consistently identified as the primary driver of threshold voltage (V_TH) instability under gate bias stress in power switching applications.
A key complexity identified in the literature is that the direction of V_TH shift is not solely determined by the sign of the gate bias, but also by which trap species and spatial locations dominate at a given bias level. TCAD simulation work from Asia University (2021) on 600 V GaN/AlGaN/GaN devices showed that precise tuning of V_TH requires control of donor-like traps at nitride/GaN interfaces at a density of ~3×10¹³ cm⁻² with energy 1.42 eV below the conduction band, as well as acceptor traps in the AlGaN layer with activation energy 0.59 eV. These parameters set the equilibrium threshold voltage and determine its sensitivity to subsequent charge redistribution under stress.
STMicroelectronics’ 2022 analytical model of V_TH recovery in fully recessed MIS-gate GaN transistors further refined this picture by distinguishing between fast interface traps and slower bulk dielectric traps. In fully recessed architectures, V_TH relaxation after voltage stress is primarily governed by charges residing near the gate dielectric/GaN interface — specifically within the dielectric itself or the GaN epitaxial layer immediately beneath the oxide. Both trap populations contribute to the transient instability observed during power switching, but with characteristically different time constants that produce the non-exponential recovery curves commonly reported in reliability studies.
“The density and energetic distribution of interface traps are both critical parameters for V_TH instability — not merely their total count. Multiple overlapping trap levels produce complex, non-exponential V_TH transients that cannot be modeled by a single time constant.”
University of Padova’s 2020 investigation of semi-vertical GaN-on-Si trench-MOSFETs under positive gate stress identified a further nuance: small negative V_TH shifts at low stress levels (attributed to trapping within the insulator bulk) and positive V_TH shifts at high stress (attributed to trapping at the metal/insulator interface). UV-assisted C-V analysis was used to extract the de-trapping threshold energy of ~2.95 eV and characterize the GaN/Al₂O₃ interface state distribution — a direct measurement technique that provides spatially resolved information about which portion of the gate stack is responsible for a given instability signature.
Measuring What You Cannot See: D_it Characterization Methods for GaN Gate Stacks
Quantitative characterization of interface trap density is essential for correlating D_it to V_TH instability severity — and the choice of technique determines whether fast interface states, slow border traps, or bulk dielectric defects are being measured. A 2023 critical review from Shanghai University surveys the applicable methods, comparing capacitance-voltage (C-V), conductance-voltage (G-V), deep-level transient spectroscopy (DLTS), and drain current transient analysis for their ability to distinguish bulk versus interface trap contributions in GaN HEMTs.
DLTS measurements on Au/AlGaN/GaN HEMT structures resolved an interface state density of 2×10¹⁰ cm⁻² eV⁻¹ with a time constant of 1 µs, alongside four distinct deep trap levels at 0.64, 0.95, 1.19, and 1.32 eV below the conduction band, each contributing a characteristic emission time constant to the slow threshold voltage recovery observed after gate stress (King Saud University, 2021).
The conductance method applied to FATFET structures by the University of Ulsan (2021) extracted a minimum D_it of 2.5×10¹² cm⁻² eV⁻¹ at the Al₀.₂₅Ga₀.₇₅N/GaN heterointerface. This value was shown to be directly consistent with the measured subthreshold swing of ~142 mV/decade in actual transistors, establishing a quantitative bridge between extracted trap density and a standard device electrical parameter. The same study characterized border traps extending into the AlGaN barrier, highlighting the need to distinguish true interface states from near-interface bulk traps when modeling V_TH instability — a distinction that becomes critical when choosing between process mitigation strategies.
Interface states reside precisely at the dielectric/semiconductor boundary and respond rapidly to gate bias changes. Border traps are located within the dielectric but close enough to the interface to exchange charge with the semiconductor over longer timescales. Both contribute to V_TH instability in GaN MIS-HEMTs, but with different time constants and energy distributions — making their separation by characterization technique critical for accurate reliability modeling.
UV-assisted C-V analysis, applied by the University of Padova (2020) to GaN/Al₂O₃ trench-MOSFET structures, offers a complementary approach: by using UV illumination to depopulate traps and comparing C-V curves before and after illumination, the technique extracts a de-trapping threshold energy (measured at ~2.95 eV in that study) and maps the interface state distribution across the bandgap. This spatially and energetically resolved information is particularly valuable for identifying whether a given process modification has shifted the trap distribution toward or away from the conduction band edge — the energetically active region for n-channel GaN HEMTs.
The importance of standardized measurement conditions cannot be overstated. According to IEEE reliability standards and the “Triple Sense” protocol developed by Univ. Lyon/INSA Lyon/CNRS (2023), conventional threshold voltage readings are corrupted by interface-trap-induced transient shifts that occur during the measurement sweep itself. The protocol, adapted from SiC MOSFET qualification practice, enables reproducible V_TH measurements despite this instability — a prerequisite for meaningful D_it-to-V_TH correlation studies and for qualifying GaN power devices to industry standards.
Explore the full patent and literature landscape for GaN HEMT interface trap characterization methods in PatSnap Eureka.
Search GaN HEMT Patents in PatSnap Eureka →How Device Architecture Shapes the V_TH Instability Profile
The gate architecture — whether p-GaN Schottky gate, MIS-HEMT, or fully recessed MOSFET-channel HEMT — fundamentally determines how interface trap density translates into V_TH instability, because each structure introduces a different set of charge-trapping interfaces and different dominant trap species. Understanding these architecture-specific mechanisms is essential for correctly attributing observed V_TH shifts to their root causes and selecting the appropriate mitigation strategy.
p-GaN Gate Devices: Vacancy-Driven Bidirectional Trapping
In p-GaN gate devices, the metal/p-GaN/AlGaN/GaN stack introduces multiple charge-trapping interfaces. Research from Consiglio Nazionale delle Ricerche (CNR-IMM, Catania) published in 2022 demonstrated that under on-state stress, both electron and hole trapping occur at distinct interfaces depending on gate bias level: electrons are trapped for V_G below 6 V (causing positive ΔV_TH) and holes are trapped for V_G above 6 V (causing negative ΔV_TH). Activation energies extracted from temperature-dependent gate current measurements correlated electron traps with nitrogen vacancies and hole traps with gallium vacancies in the p-GaN layer — providing a direct chemical identity for the dominant trap species in this architecture.
Temperature amplifies this effect significantly. Nanjing University’s 2022 investigation of Schottky gate (SG) and Ohmic gate (OG) p-GaN devices under temperature-dependent negative gate bias stress found qualitatively different thermal behaviours: SG devices exhibited a concave-shaped V_T evolution with increasing temperature, while OG devices showed a different pattern due to differing trap emission kinetics. This temperature dependence is a critical reliability concern for high-temperature power applications where GaN devices are expected to operate, according to reliability frameworks published by JEDEC.
MIS-HEMT Architectures: Dielectric Interface as the Primary Instability Site
In MIS-HEMT architectures, the gate oxide introduces additional interface states not present in Schottky or p-GaN gate devices. National Chiao-Tung University (2017) showed that under high applied electric fields, traps at the dielectric/III-N barrier interface and within the III-N barrier cause both dynamic on-resistance increase and V_TH shift. Importantly, the dielectric interface trap population grows under repeated high-field stress, progressively worsening V_TH stability over device lifetime — a cumulative degradation mode distinct from the recoverable trapping seen under single-pulse stress conditions.
In p-GaN gate GaN HEMTs, nitrogen vacancies act as electron traps causing positive threshold voltage shifts at gate voltages below 6 V, while gallium vacancies act as hole traps causing negative threshold voltage shifts at gate voltages above 6 V, as identified by CNR-IMM Catania (2022) through activation energy analysis of temperature-dependent gate current measurements.
Fully Recessed MIS-Gate: Etch-Induced Defects as the Fundamental Barrier
For fully recessed MIS-gate structures, CEA-Leti’s 2023 review identifies mandatory AlGaN barrier etching as a primary source of etching-related defects, roughness, and interface traps that lead to unstable V_TH and reduced electron mobility. The etching process physically damages the GaN surface that will subsequently serve as the gate dielectric/semiconductor interface, creating a high baseline D_it that is difficult to reduce by post-etch treatment alone. This is the central challenge limiting the commercial deployment of fully recessed enhancement-mode GaN power switches, according to PatSnap’s wide-bandgap semiconductor research resources.
Carbon Buffer Coupling: A Multi-Layer Challenge
Carbon doping in the GaN buffer — widely used to suppress buffer leakage in high-voltage GaN-on-Si devices — adds an indirect pathway for interface-trap-driven V_TH instability. University of Modena and Reggio Emilia’s 2020 numerical device simulations demonstrated that carbon-related acceptor traps in the GaN buffer attract free holes to the device surface under negative gate bias, where they are captured into interface traps or recombine with gate-injected electrons. This carbon-to-interface trap coupling means that buffer design choices directly influence gate dielectric interface trap behaviour, making device optimization a genuinely multi-layer challenge that cannot be addressed by gate stack engineering alone.
Suzhou University of Science and Technology (2024) identified that in PZT/Al₂O₃ bilayer gate stacks, the large dielectric constant mismatch between PZT and Al₂O₃ concentrates the electric field at the Al₂O₃/GaN interface and accelerates in-situ trap creation under positive gate bias stress. This demonstrates that V_TH instability in ferroelectric-gate GaN HEMTs is not merely a function of pre-existing D_it, but also of ongoing trap generation during device operation — a distinct and more severe reliability mode.
Process and Materials Strategies to Suppress D_it and Stabilise V_TH
Reducing interface trap density at the gate dielectric/GaN boundary is the most direct route to V_TH stabilisation, and the literature documents several process and materials strategies with quantified outcomes. The most experimentally rigorous demonstration comes from NaMLab/TU Dresden (2020): applying O₂ plasma surface preconditioning before atomic layer deposition of Al₂O₃, followed by N₂ post-metallization annealing, reduced D_it at the Al₂O₃/GaN interface to the order of 2×10¹² cm⁻² eV⁻¹ near the conduction band edge, with a directly measurable improvement in V_TH stability under positive gate bias stress. This result establishes a causal chain between a specific process sequence and a quantified D_it reduction with a corresponding V_TH benefit.
Hokkaido University’s 2018 state-of-the-art review of gate insulation and surface passivation for GaN power HEMTs evaluated dielectric choices including Al-based oxides, SiNx, SiO₂, and high-k dielectrics. The review found that in-situ SiNx and surface oxidation of (Al)GaN achieved the best combination of DC performance and stable V_TH. Critically, the review also noted that interface trap-induced sudden current saturation under forward gate bias is a distinctive failure mode in GaN MIS-HEMTs directly attributable to D_it magnitude — meaning that D_it reduction is not only a reliability metric but also a performance metric. Nanolaminate gate dielectric structures were highlighted as a promising design approach for combining the benefits of multiple dielectric materials while minimising interfacial defect density at each layer boundary, consistent with guidance from Semiconductor Digest on advanced gate stack engineering.
For fully recessed MIS-gate structures, CEA-Leti’s 2023 review identifies selective etch chemistries, in-situ passivation immediately after etching, and dielectric optimization as the three-pronged approach required to suppress etch-induced D_it. The review notes that etching-related defects, surface roughness, and interface traps from the mandatory AlGaN barrier etch are the primary barrier to commercial deployment of fully recessed GaN power switches — a conclusion consistent with the broader wide-bandgap power device reliability framework documented by IEC standards bodies.
Map the patent landscape for GaN HEMT gate dielectric process innovations — find assignees, filing trends, and white-space opportunities.
Explore GaN Power Device Patents in PatSnap Eureka →Research Landscape and Innovation Trends in GaN HEMT Gate Dielectric Engineering
The research landscape for GaN HEMT interface trap density and V_TH instability has evolved through three distinct phases, based on the publication record spanning more than 50 sources from 2013 to 2025. Understanding which institutions lead each phase — and where the current frontier lies — is essential for R&D teams positioning their own work and for IP professionals assessing the competitive landscape.
Leading Research Groups and Their Contributions
The University of Padova is the most prolific contributor to this field in the dataset, with multiple papers spanning p-GaN gate trapping, OFF-state and ON-state stress mechanisms, semi-vertical GaN trench-MOSFET V_TH instability, and buffer trapping kinetics. Their work covers the full spectrum from basic trap identification through quantitative characterization to degradation mechanism modeling, making their publication record an essential reference for anyone entering this field.
NaMLab/TU Dresden provides the most direct experimental quantification of D_it reduction via process improvements and its effect on V_TH stability, establishing the O₂ plasma preconditioning plus N₂ post-metallization annealing sequence as a benchmark process. CEA-Leti contributes the most comprehensive review of fully recessed MIS gate technology, focusing on process-related D_it as the key barrier to commercial deployment. Hokkaido University provides the most extensive review of dielectric materials choices for GaN MIS-HEMTs, while STMicroelectronics (Catania) contributes the analytical V_TH recovery model for fully recessed MIS-HEMTs that bridges experimental observation and circuit-level reliability prediction.
Three-Phase Innovation Trajectory
The innovation trajectory visible in the data shows a clear progression. The pre-2018 phase focused on basic identification of trapping mechanisms — establishing which interfaces trap charge and in which direction. The 2018–2021 phase shifted to quantitative D_it characterization and process optimization, with multiple groups reporting specific D_it values and linking them to measurable device parameters. The current phase (2021–2024) is characterized by analytical and TCAD models for V_TH recovery prediction, novel device architectures (including ferroelectric gate stacks and semi-vertical trench structures), and standardization efforts for measurement protocols.
The “Triple Sense” V_TH measurement protocol, adapted from SiC MOSFET qualification practice by Univ. Lyon/INSA Lyon/CNRS (2023), enables reproducible threshold voltage measurements in GaN HEMTs despite interface-trap-induced transient V_TH shifts that corrupt conventional measurement sweeps — providing a practical standardization approach for GaN power device qualification.
Notable patent activity from Chinese institutions — including the University of Electronic Science and Technology of China, Beijing University of Technology, and Nanjing-based institutes — focuses on modeling threshold voltage drift as a function of switching frequency and drain-source voltage, and on developing novel trap characterization methods based on drain-source resistance transients and voltage transient responses. This activity reflects the broader commercial urgency around GaN power device reliability as Chinese manufacturers scale GaN power IC production, consistent with market trends tracked by PatSnap’s innovation intelligence platform.
The convergence of analytical modeling, TCAD simulation, and standardized measurement protocols in the most recent literature suggests that the field is transitioning from a research-dominated phase to a pre-standardization phase — where the fundamental physics are sufficiently understood to begin codifying reliability test methods and process specifications for commercial qualification. For IP professionals, this transition signals an opportunity to file process and characterization method patents before industry standards lock in specific approaches, as has historically occurred in Si CMOS and SiC MOSFET qualification according to frameworks documented by WIPO.