Atomic Layer Deposition for Semiconductor Processing 2026
Atomic Layer Deposition for Semiconductor Processing
ALD is expanding from high-k gate dielectrics into area-selective patterning, 3D wafer bonding, and integrated ALD/ALE workflows. This landscape covers 40+ patent records spanning 1992–2025.
ALD: Angstrom-Level Control for Sub-5 nm Semiconductor Nodes
Atomic layer deposition operates through sequential, self-limiting surface reactions where alternating precursor pulses deposit a single atomic monolayer per cycle. This yields sub-nanometer thickness control and conformal coverage on topographically complex surfaces — properties that differentiate ALD from CVD and PVD and make it indispensable at sub-5 nm device geometries.
The dataset reveals six active ALD sub-domains in semiconductor processing: thermal ALD, plasma-enhanced ALD (PE-ALD), atmospheric-pressure spatial ALD (AP-SALD), electrochemical ALD (EC-ALD), area-selective ALD (AS-ALD), and integrated ALD/ALE processes. Each addresses specific constraints — temperature sensitivity, throughput, selectivity, or substrate compatibility.
ALD achieves conformal deposition on high-aspect-ratio structures including trenches and vias with aspect ratios of 40:1 or more, at temperatures ranging from room temperature to approximately 400°C. This combination of conformality and low thermal budget is central to its role in FinFET, gate-all-around (GAA) transistor, and 3D NAND fabrication.
The patent landscape spans more than three decades, from Fujitsu Limited’s foundational compound semiconductor epitaxy filings in 1993 through TSMC’s 2025-active plasma-ALD work function metal patents. The field is moderately concentrated: Samsung, TSMC, Lam Research, Applied Materials, and SMIC collectively account for the largest share of commercially active patents in this dataset.
ALD Innovation Phases: From Compound Semiconductors to 3D Integration
The ALD patent dataset spans three distinct innovation phases from 1992 to 2025, reflecting the technology’s evolution from foundational epitaxy concepts to advanced process integration for sub-5 nm nodes and 3D chiplet architectures.
ALD Technology Clusters by Patent Count in Dataset
The Thermal/PE-ALD for high-k dielectrics cluster is the largest in the dataset, followed by ALD/ALE integration and high-aspect-ratio gap-fill approaches.
↗ Click bars to exploreALD Patent Filings by Innovation Phase (Dataset Records)
Filing activity accelerated markedly in the 2016–2025 advanced process integration phase, driven by ALD/ALE integration, 3D bonding layer, and Chinese domestic equipment patents.
↗ Click bars to exploreWhere ALD Is Applied: From Gate Stacks to Advanced Packaging
ALD serves multiple distinct application domains in semiconductor manufacturing, each exploiting its unique conformality and thickness-control properties. The dataset covers domains ranging from advanced logic gate engineering to post-fabrication passivation and chiplet bonding.
Advanced Logic and FinFET/GAA Nodes
TSMC’s plasma-ALD patents (US, 2023–2025) cover reactive-gas plasma deposition of work function metal layers for advanced gate stacks, including a 2025-active filing. Samsung Electronics’ alloy layer ALD (US, 2020) and Alsephina Innovations’ atomic layer doping at concentrations ≥4×10²⁰ atoms/cm³ (US, 2013) anchor this domain. GlobalFoundries’ low-temperature ALD (below 400°C) for germanium-containing substrates targets transistor gate structures for heterogeneous logic.
Gate Stack / Logic3D NAND and High-Aspect-Ratio Memory
Sungkyunkwan University’s 2024 US pending patent describes multi-pulse ALD enabling void-free gap-fill in structures with aspect ratios of 40:1 or higher, removing overhangs simultaneously — directly addressing 3D NAND memory cell fabrication challenges. ALD’s conformality in high-aspect-ratio structures is also documented in multiple literature sources referencing FinFET and 3D-NAND contexts. Conventional ALD faces overhang-related failure modes in these structures that multi-pulse approaches resolve.
3D NAND / DRAMAdvanced Packaging and 3D Chiplet Bonding
TSMC filed two patents (US, 2023 and 2024) on ALD bonding layers deposited on two device surfaces and fused by annealing for 3D wafer integration — a new application of ALD outside traditional thin-film deposition roles. This enables precision bonding interfaces for chiplet-based architectures and high-bandwidth memory stacking. The 2024 filing is a continuation of the 2023 family, indicating active IP development in this area.
Advanced PackagingChip Reliability and Passivation Coatings
A 2022 study demonstrated that a 15 nm Al₂O₃ coating deposited by room-temperature ALD measurably improved humidity and wear resistance of production 14 nm HPC ASICs. ALD passivation is also documented for micro-LEDs and VCSELs (2021 literature), where it enhances light efficiency, reduces leakage current, and improves device reliability relevant to display and optical interconnect manufacturing. These applications exploit ALD’s low thermal budget for post-fabrication use.
Passivation / ReliabilityLeading ALD Patent Holders in Semiconductor Processing
The ALD patent landscape is moderately concentrated, with Samsung, TSMC, Lam Research, Applied Materials, and SMIC collectively holding the largest share of commercially active patents in this dataset. TSMC leads in recent filings with five US patents spanning 2013–2025.
Top ALD Patent Assignees by Filing Count in Dataset
↗ Click bars to exploreTaiwan Semiconductor Manufacturing Company
TSMC holds five US patents in this dataset spanning 2013–2025, covering ultra-shallow junctions via atomic-layer doping (2013), work function metal PE-ALD for gate stacks (2023 active, 2025 active), and ALD bonding layers for 3D wafer-to-wafer joining (2023 and 2024 active). The 2025 filing on plasma-ALD reactive-gas treatment for gate metal layers represents TSMC’s leading-edge gate engineering IP. TSMC’s ALD bonding layer patents (2023–2024) mark a strategic extension into advanced 3D chiplet packaging.
United States / TaiwanLam Research Corporation
Lam Research holds four active US patents in this dataset, forming a continuous patent family from 2016 through 2019 covering the integration of ALD and ALE within a single chamber for atomic-scale build-and-etch manufacturing workflows. This cluster — titled “Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)” — represents the dominant assignee in combined ALD/ALE process architecture. All four patents are active US grants, signaling a well-defended IP position in this process segment.
United StatesNext-Generation ALD: Six Directions Gaining Momentum in 2021–2025
Based on the most recent filings and publications in this dataset (2021–2025), six directions are gaining clear momentum — from high-aspect-ratio gap-fill for 3D memory to Chinese domestic ALD equipment development and room-temperature passivation for advanced packaging.
Multi-Pulse ALD for 40:1 Aspect Ratio Gap-Fill in 3D NAND
Sungkyunkwan University’s 2024 US pending patent introduces multi-pulse ALD that enables void-free filling of structures with aspect ratios of 40:1 or higher, removing overhangs simultaneously. This directly addresses process failure modes where conventional single-pulse ALD creates voids or seams in 3D NAND flash and advanced DRAM architectures. The filing is a direct response to the vertical scaling demands of next-generation memory fabrication.
ALD Bonding Layers Enable 3D Chiplet and Wafer-to-Wafer Integration
TSMC’s two-patent family (US, 2023 and 2024) on ALD bonding layers deposited on device surfaces and fused by annealing represents a genuinely new application of ALD outside traditional thin-film deposition. These patents target die-to-die and wafer-to-wafer bonding for chiplet architectures and high-bandwidth memory, a market growing rapidly with chiplet adoption. Competitors and entrants in advanced packaging should assess freedom-to-operate against this emerging cluster.
Thermal ALD vs. Plasma-Enhanced ALD: Key Process Dimensions
Click any row to explore further.
| Dimension | Thermal ALD | Plasma-Enhanced ALD (PE-ALD) |
|---|---|---|
| Process Temperature | 200–400°C (typical range) | Room temperature to ~400°C; lower temperatures accessible |
| Surface Reaction Mechanism | Sequential precursor/oxidant thermal cycles | Reactive plasma species replace thermal oxidant pulses |
| Film Density | Standard; lower density at lower temperatures | Improved film density and reactivity vs. thermal ALD |
| Key Materials Deposited | HfO₂, Al₂O₃, ZrO₂, Y₂O₃, SiO₂ (gate dielectrics) | Work function metals, WS₂, MoS₂, 2D transition metal dichalcogenides |
| Representative Assignee | GlobalFoundries (SiO₂ on Ge below 400°C, US 2018) | TSMC (reactive-gas plasma work function layers, US 2023/2025) |
| Temperature Budget Suitability | Constrained by 400°C upper limit for back-end integration | Better for temperature-sensitive substrates and 3D integration |
| Conformality | Excellent; demonstrated at 40:1 aspect ratio | Excellent; validated on complex 3D gate-all-around structures |
| 2D Material Deposition | Not documented in dataset for 2D materials | AS-ALD of WS₂ at 250°C demonstrated (literature, 2020) |
Frequently Asked Questions: Atomic Layer Deposition in Semiconductor Processing
ALD operates through sequential, self-limiting surface reactions where alternating precursor pulses each deposit a single atomic monolayer. This yields sub-nanometer thickness control and conformal coverage on topographically complex surfaces — including trenches and vias with aspect ratios of 40:1 or more — at temperatures from room temperature to approximately 400°C. CVD and PVD do not offer the same degree of self-limiting thickness control or conformality on high-aspect-ratio structures.
Plasma-enhanced ALD (PE-ALD) replaces the thermal oxidant pulse with reactive plasma species, extending the process window to lower temperatures, improving film density and reactivity. TSMC’s active US patents (2023, 2025) cover plasma-ALD of work function metal layers using reactive-gas plasma treatment cycles for advanced gate stacks in FinFET and gate-all-around transistors. PE-ALD is also used for 2D materials such as WS₂ deposition at 250°C.
Area-selective ALD (AS-ALD) deposits material only on designated surfaces using inhibitor molecules to block deposition on non-target areas, enabling bottom-up self-aligned nanofabrication. This approach directly reduces edge placement errors inherent in EUV lithographic patterning — a fundamental scaling limiter at sub-5 nm nodes. Literature evidence from 2018–2020 shows ABC-type plasma-enhanced AS-ALD of WS₂ at 250°C using acetylacetone inhibitors, with rapid process development reported.
ALD’s conformality in high-aspect-ratio structures makes it the enabling deposition technology for 3D NAND flash. The Sungkyunkwan University 2024 US pending patent describes multi-pulse ALD that enables void-free gap-fill in structures with aspect ratios of 40:1 or higher, removing overhangs simultaneously. Conventional single-pulse ALD can create voids or seams in these structures, making multi-pulse approaches a critical process advance for 3D memory architectures.
TSMC filed two US patents (2023 and 2024) on ALD bonding layers deposited on device surfaces and fused by annealing for 3D wafer integration. These patents target die-to-die and wafer-to-wafer bonding for chiplet architectures and high-bandwidth memory — a relatively new application of ALD outside traditional thin-film deposition roles. The 2024 filing is a continuation of the 2023 family, indicating active IP development.
Multiple 2021–2025 CN patents from Chinese semiconductor equipment firms — including Wuxi Yiwen Microelectronics Technology (two CN patents, 2021–2022), Shanghai Jita Semiconductor (2025 pending), and Xin’en (Qingdao) Integrated Circuit Co. (CN, 2024 active) — describe complete ALD system architectures including multi-chamber vacuum platforms, thermal ALD reactors, and matrix-array chamber configurations. This cluster reflects a strategic push toward ALD equipment self-sufficiency within China’s semiconductor supply chain.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.